XR16C864 Datasheet, PDF (29/51 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

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REV. 2.0.1
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
TABLE 11: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCTR FCTR FCR
BIT-5 BIT-4 BIT-7
0
0
0
0
1
1
0
1
0
0
1
1
1
0
0
0
1
1
1
1
X
FCR
BIT-6
0
1
0
1
0
1
0
1
0
1
0
1
X
FCR
BIT-5
0
0
0
1
1
0
0
1
1
X
FCR
RECEIVE
BIT-4 TRIGGER LEVEL
TRANSMIT
TRIGGER
LEVEL
COMPATIBILITY
0
1 (default) Table-A. 16C550, 16C2550,
1 (default)
4
16C2552, 16C554, 16C580
compatible.
8
14
0
1
0
1
8
16
24
28
16
Table-B. 16C650A compatible.
8
24
30
0
1
0
1
8
16
56
60
8
Table-C. 16C654 compatible.
16
32
56
X Programmable Programmable Table-D. 16L2750, 16C2850,
via TRG
register.
via TRG
register.
16C2852, 16C850, 16C864
compatible.
FCTR[7] = 0. FCTR[7] = 1.
4.6 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
0
0
1
1
BIT-0
0
1
0
1
WORD LENGTH
5 (default)
6
7
8
29