XR16C864 Datasheet, PDF (13/51 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

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REV. 2.0.1
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
frequencies are: 1.8432, 3.6864, 7.3728, 14.7456, 18.432, and 22.1184 MHz. Alternatively, an external clock
can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates.
Typical oscillator connections are shown in Figure 4. For further reading on oscillator circuit please see
application note DAN108 on EXAR’s web site.
2.11 Programmable Baud Rate Generator
Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a
software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external
clock by 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a
programmable divisor between 1 and (2¹⁶ -1) to obtain a 16X sampling rate clock of the serial data rate. The
sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling.
FIGURE 5. BAUD RATE GENERATOR AND PRESCALER
XTAL1
XTAL2
C rystal
Osc/
B u ffe r
P re s ca le r
D ivide by 1
P re s ca le r
D ivide by 4
DLL and DLM
R egisters
M C R Bit-7=0
(d e fa u lt)
Baud Rate
G enerator
L o g ic
M C R Bit-7=1
16X
Sam pling
R ate C lock to
Transm itter
Table 6 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate OUTPUT Data Rate
MCR Bit-7=1
MCR Bit-7=0 ^{DIVISOR FOR 16x DIVISOR FOR 16x}
Clock (Decimal) Clock (HEX)
(DEFAULT)
DLM
PROGRAM
VALUE (HEX)
DLL
PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
100
400
2304
900
09
00
0
600
2400
384
180
01
80
0
1200
4800
192
C0
00
C0
0
2400
9600
96
60
00
60
0
4800
19.2k
48
30
00
30
0
9600
38.4k
24
18
00
18
0
19.2k
76.8k
12
0C
00
0C
0
38.4k
153.6k
6
06
00
06
0
57.6k
230.4k
4
04
00
04
0
115.2k
460.8k
2
02
00
02
0
230.4k
921.6k
1
01
00
01
0
2.12 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 128 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
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