XR19L402 Datasheet, PDF (50/50 Pages) Exar Corporation – TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER

XR19L402
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
REV. 1.0.0
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 24
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 24
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 25
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 25
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 26
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 26
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 26
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 28
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 28
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 29
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE.. 30
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 31
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 32
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 33
4.11 ENHANCED MODE SELECT REGISTER (EMSR) ......................................................................................... 33
TABLE 12: SCRATCHPAD SWAP SELECTION .................................................................................................................................... 33
TABLE 13: XON/XOFF HYSTERESIS .............................................................................................................................................. 33
4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY............................................................................................. 34
4.13 BAUD RATE GENERATOR REGISTERS (DLL, DLM AND DLD) - READ/WRITE ....................................... 34
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY....................................................................... 34
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY ................................................................................. 34
4.16 TRIGGER LEVEL REGISTER (TRG) - WRITE-ONLY .................................................................................... 34
4.17 RX/TX FIFO LEVEL COUNT REGISTER (FC) - READ-ONLY ....................................................................... 35
4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE........................................................................... 35
TABLE 14: TRIGGER TABLE SELECT ................................................................................................................................................ 35
4.19 ENHANCED FEATURE REGISTER (EFR) ..................................................................................................... 36
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 36
4.19.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE .............................. 37
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B ............................................................................................ 38
ABSOLUTE MAXIMUM RATINGS.................................................................................. 39
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 39
AC ELECTRICAL CHARACTERISTICS ............................................................................................................. 40
Unless otherwise noted: TA=-40o to +85oC, Vcc=3.3 or 5V ± 10%, 70 pF load where applicable.......................... 40
FIGURE 12. CLOCK TIMING............................................................................................................................................................. 41
FIGURE 13. MODEM INPUT/OUTPUT TIMING .................................................................................................................................... 42
FIGURE 14. 16 MODE (INTEL) DATA BUS READ TIMING ................................................................................................................... 43
FIGURE 15. 16 MODE (INTEL) DATA BUS WRITE TIMING.................................................................................................................. 43
FIGURE 16. 68 MODE (MOTOROLA) DATA BUS READ TIMING .......................................................................................................... 44
FIGURE 17. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING......................................................................................................... 44
FIGURE 18. RECEIVE READY INTERRUPT TIMING [NON-FIFO MODE] ............................................................................................... 45
FIGURE 19. TRANSMIT READY INTERRUPT TIMING [NON-FIFO MODE] ............................................................................................. 45
FIGURE 20. RECEIVE READY INTERRUPT TIMING [FIFO MODE] ....................................................................................................... 46
FIGURE 21. TRANSMIT READY INTERRUPT TIMING [FIFO MODE] ..................................................................................................... 46
PACKAGE DIMENSIONS................................................................................................ 47
REVISION HISTORY...................................................................................................................................... 48
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