XR19L402 Datasheet, PDF (15/50 Pages) Exar Corporation – TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER

XR19L402
REV. 1.0.0
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
2.11.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
2.11.2 Selectable Input to RX of Channel B
There is an input (RXBSEL) that selects whether the signal going to the RXB input of the UART will be the
signal from the RS-485 transceiver or not. If RXBSEL is LOW, then the signal to the RXB input is the RXB+
and RXB- signals from the RS-485 transceiver. When RXB+ and RXB- are used, the RXB input should be left
floating. The signal received at the UART can be probed at the RXB pin. If RXBSEL is HIGH, then the RXB+
and RXB- pins are tri-stated and RXB can be used with an external Infrared transceiver or RS-232 transceiver.
If RXB is selected but is unused, RXB should be connected to VCC. See Figure 6 for a detailed drawing.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
16X or 8X Clock
(EMSR bit-7)
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Receive
Data Byte
and Errors
Error
Tags in
LSR bits
4:2
Receive Data
Holding Register
(RHR)
RHR Interrupt (ISR bit-2)
RXFIFO1
2.12 Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 15), the L402 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the L402 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the L402 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the L402 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters (See Table 15) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters
are selected, the L402 compares two consecutive receive characters with two software flow control 8-bit
values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow
control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or
FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the L402 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The L402 sends the
Xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate)
after the receive FIFO crosses the programmed trigger level (for all trigger tables A-D). To clear this condition,
the L402 will transmit the programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger
level below the programmed trigger level (for Trigger Tables A, B, and C) or when receive FIFO is less than the
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