XR16C864IQ-F Datasheet, PDF (5/51 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

REV. 2.2.0
Pin Description
XR16C864
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
NAME
100-QFP
TYPE
PIN #
DESCRIPTION
FSRS#
76
I FIFO Status Register Select (active low input with internal pull-up).
The content of the FSTAT register is placed on the data bus when this pin becomes
active. However it should be noted, D0-D3 contain the inverted logic states of TXRDY#
A-D pins, and D4-D7 the logic states (un-inverted) of RXRDY# A-D pins. Address line is
not required when reading this status register.
DIRECT MEMORY ACCESS INTERFACE
TC
54
I Direct Memory Access Terminal Count. A high pulse terminates a Direct Memory Access
transaction. If Direct Memory Access is not used, this input should be connected to GND.
AEN
27
I Address Enable for Direct Memory Access. A high at this input indicates a valid Direct
Memory Access cycle. See DACK pin descriptions below for Direct Memory Access cycle
description. If Direct Memory Access is not used, this input should be connected to GND.
DACKA
4
I Direct Memory Access Acknowledge. Direct Memory Access cycle will start processing
DACKB
26
when CPU/Host sets this input low and AEN high. All writes will be to the TX FIFO and all
DACKC
55
DACKD
77
reads will be from the RX FIFO. A0-A2 and CS# A-D will be ignored. If Direct Memory
Access is not used, these inputs should be connected to VCC.
TXDRQA
5
TXDRQB
25
TXDRQC
56
TXDRQD
81
O Transmit Direct Memory Access Request. A transmit empty request is indicated by a high
level on TXDRQ. The TXDRQ line is held high until either TC pulses or the TX FIFO is
filled above its trigger level. Transmit Direct Memory Access Request is enabled by set-
ting EMSR register bit-2 = 1. If Direct Memory Access is not used, leave these outputs
unconnected.
RXDRQA 100
RXDRQB
31
RXDRQC
50
RXDRQD
82
O Receive Direct Memory Access Request. A Receive ready request is indicated by a high
level on RXDRQ. The RXDRQ line is held high until either TC pulses or the RX FIFO is
emptied. Receive Direct Memory Access Request is enabled by setting EMSR register
bit-3 = 1. If Direct Memory Access is not used, leave these outputs unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA
TXB
TXC
TXD
14
O UART channels A-D Transmit Data and infrared transmit data. Standard transmit and
16
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be a logic
65
1 during reset, or idle (no data). Infrared IrDA transmit and receive interface is enabled
67
when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0.
IRTXA
IRTXB
IRTXC
IRTXD
6
O UART channels A-D Infrared Transmit Data. The inactive state (no data) for the Infrared
24
encoder/decoder interface is a logic 0. Regardless of the logic state of MCR bit-6, this pin
57
will be operating in the Infrared mode.
75
RXA
RXB
RXC
RXD
97
I UART channels A-D Receive Data or infrared receive data. Normal receive data input
34
must idle at logic 1 condition. The infrared receiver pulses typically idles at logic 0 but can
47
be inverted by software control prior going in to the decoder, see FCTR[2].
85
RTSA#
RTSB#
RTSC#
RTSD#
11
O UART channels A-D Request-to-Send (active low) or general purpose output. This output
19
must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1], FCTR[1:0],
62
EMSR[5:4] and IER[6]. Also see Figure 10. If these outputs are not used, leave them
70
unconnected.
5