XR16V654_0709 Datasheet, PDF (49/58 Pages) Exar Corporation – 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO

REV. 1.0.2
XR16V654/654D
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
FIGURE 24. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D
RX
INT
RXRDY#
Start
Bit
Stop
Bit
S D0:D7 S D0:D7 T
D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T
T_SSI
RX FIFO drops
below RX
Trigger Level
RX FIFO fills up to RX
Trigger Level or RX Data
T_SSR
Timeout
FIFO
Empties
IOR#
(Reading data out
of RX FIFO)
T_RRI
T_RR
RXFIFODMA
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D
TX FIFO
Empty
TX
(Unloading)
INT*
IER[1]
enabled
TXRDY#
Data in
TX FIFO
Start
Bit
Stop
Bit
S D0:D7 T
ISR is read
S D0:D7 T S D0:D7 T T S D0:D7 T S D0:D7 T
T_SI
ISR is read
TX FIFO fills up
to trigger level
T_WT
T_WRI
TX FIFO drops
below trigger level
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
Last Data Byte
Transmitted
S D0:D7 T
T_SRT
TX FIFO
Empty
TXDMA#
49