XR16V654_0709 Datasheet, PDF (28/58 Pages) Exar Corporation – 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO

XR16V654/654D
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
REV. 1.0.2
TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
Enhanced Registers
010
100
EFR
RD/WR Auto
CTS#
Enable
Auto
RTS#
Enable
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5],
DLD
XON1 RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Soft-
ware
Flow
Cntl
Bit-3
Bit-3
Soft-
ware
Flow
Cntl
Bit-2
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
LCR=0XBF
Bit-0
1 0 1 XON2 RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
1 1 0 XOFF1 RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
1 1 1 XOFF2 RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
X X X FSTAT RD
RX-
RX-
RX-
RX-
TX-
TX- TX- TX- FSRS# pin is
RDYD# RDYC# RDYB# RDYA# _RDYD# RDYC# RDYB# RDYA# ^{a logic 0. No}
address lines
required.
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
SEE”RECEIVER” ON PAGE 19.
4.2 Transmit Holding Register (THR) - Write-Only
SEE”TRANSMITTER” ON PAGE 17.
4.3 Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.3.1 IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
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