XR16V654_0709 Datasheet, PDF (27/58 Pages) Exar Corporation – 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO

XR16V654/654D
REV. 1.0.2
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
IER RD/WR 0/
0/
0/
CTS#
Int.
Enable
RTS#
Int.
Enable
Xoff Int.
Enable
0/
Sleep
Mode
Enable
Modem
Stat. Int.
Enable
RX Line
Stat.
Int.
Enable
TX
Empty
Int
Enable
RX
Data
Int.
Enable
0 1 0 ISR RD FIFOs FIFOs
0/
0/
INT
INT INT INT _{LCR[7] = 0}
Enabled Enabled
Source Source Source Source
INT
INT
Bit-3 Bit-2 Bit-1 Bit-0
Source Source
Bit-5
Bit-4
010
FCR
WR RXFIFO RXFIFO 0/
0/
Trigger Trigger
TXFIFO TX FIFO
Trigger Trigger
DMA
Mode
Enable
TX
FIFO
Reset
RX FIFOs
FIFO Enable
Reset
011
LCR RD/WR Divisor Set TX Set
Enable Break _Parity
Even
Parity
Parity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
100
MCR RD/WR
0/
BRG
Pres-
caler
0/
0/
IR Mode XonAny
ENable
Internal
Lopback
Enable
INT Out-
put
Enable
(OP2#)
Rsvd
(OP1#)
RTS#
Output
Control
DTR#
Output
Control
1 0 1 LSR RD RX FIFO THR & THR RX Break RX Fram- RX
RX
RX
Global TSR Empty
ing Error Parity Over- Data LCR[7] = 0
Error Empty
Error run Ready
Error
110
111
000
001
010
MSR RD
CD#
Input
SPR RD/WR Bit-7
DLL RD/WR Bit-7
DLM RD/WR Bit-7
DLD RD/WR Rsvd
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Bit-6 Bit-5
Bit-4
Bit-3
Baud Rate Generator Divisor
Bit-6 Bit-5
Bit-4
Bit-3
Bit-6 Bit-5
Bit-4
Bit-3
Rsvd 4X Mode 8X Mode Bit-3
Delta
RI#
Bit-2
Delta
DSR#
Bit-1
Delta
CTS#
Bit-0
Bit-2
Bit-2
Bit-2
Bit-1
Bit-1
Bit-1
Bit-0 LCR[7]=1
LCR≠0xBF
Bit-0
Bit-0
LCR[7] = 1
LCR≠0xBF
EFR[4] = 1
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