XR16L784 Datasheet, PDF (47/52 Pages) Exar Corporation – HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART

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REV. 1.2.0
XR16L784
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
FIGURE 22. TRANSMIT INTERRUPT TIMING [NON-FIFO MODE]
TX
(U nloading)
IE R [1]
e n a b le d
IN T # *
T_{W RI}
S tart
B it
D 0:D 7
S top
B it
ISR is read
T_{W RI}
D 0:D 7
ISR is read
T_{W RI}
D 0:D 7
ISR is read
IOW #
(Loading data
into TH R )
*TX interrupt is cleared w hen the IS R is read or w hen data is loaded in to the TH R .
FIGURE 23. RECEIVE INTERRUPT TIMING [FIFO MODE]
Start
Bit
RX
S D0:D7 S D0:D7 T
D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T
INT#
T_SSI
RX FIFO fills up to RX
Trigger Level or RX Data
Tim eo ut
RX FIFO drops
below RX
Trigger Level
T_RRI
T_RR
IOR#
(Reading data out
of RX FIFO)
FIGURE 24. TRANSMIT INTERRUPT TIMING [FIFO MODE]
TX FIFO
Em pty
TX
(Unloading)
INT#*
IER[1]
enabled
IOW #
(Loading data
into FIFO)
Start
Bit
Stop
Bit
S D0:D7 T
ISR is read
S D0:D7 T S D0:D7 T
T S D0:D7 T S D0:D7 T
T_SI
ISR is read
TX FIFO fills up
to trigger level
T_WRI
TX FIFO drops
below trigger level
*TX interrupt is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
Last Data Byte
T ran s m itte d
S D0:D7 T
47