XR16L784 Datasheet, PDF (19/52 Pages) Exar Corporation – HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART

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REV. 1.2.0
XR16L784
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
3.0 XR16L784 REGISTERS
The XR16L784 quad UART register set consists of the Device Configuration Registers that are accessible
directly from the data bus for programming general operating conditions of the UARTs and monitoring the
status of various functions. These functions include all 4 channel UART’s interrupt control and status, 16-bit
general purpose timer control and status, sleep mode, soft-reset, and device identification and revision. Also,
each UART channel has its own set of internal UART Configuration Registers for its own operation control,
status reporting and data transfer. These registers are mapped into a 256-byte of the data memory address
space. The following paragraphs describe all the registers in detail.
FIGURE 13. THE XR16L784 REGISTERS MAPPING
8-bit Data
Bus
Interface
Channel 0
Channel 1
Channel 2
Channel 3
INT0, INT1, INT2,
INT3, TIMER,
SLEEP, RESET
0x00-0F
0x10-1F
0x20-2F
0x30-3F
UART[3:0] Configuration Registers
16550 Compatible and
Exar Enhanced Registers
0x40-7F
(reserved)
0x80-8F
Device Configuration Registers
4 channel Interrupts,
16-bit Timer/Counter,
Sleep, Reset, DVID, DREV
784REGS
3.1 DEVICE CONFIGURATION REGISTER SET
The device configuration registers are directly accessible from the bus. This provides easy programming of
general operating parameters to the 784 UART and for monitoring the status of various functions. The device
configuration registers are mapped onto address 0x80-8F as shown on the register map in Table 8 and
Figure 13. These registers provide global controls and status of all 4 channel UARTs that include interrupt
status, 16-bit general purpose timer control and status, 8X or 16X sampling clock, sleep mode control, soft-
reset control, simultaneous UART initialization, and device identification and revision.
.
TABLE 7: XR16L784 REGISTER SETS
ADDRESS [A7:A0]
UART CHANNEL SPACE
REFERENCE
COMMENT
0x00 - 0x0F
UART channel 0 Registers
(Table 11 & 12)
First 8 registers are 16550 compatible
0x10 - 0x1F
UART channel 1 Registers
(Table 11 & 12)
0x20 - 0x2F
UART channel 2 Registers
(Table 11 & 12)
0x30 - 0x3F
UART channel 3 Registers
(Table 11 & 12)
0x40 - 0x7F
None
Reserved
0x80 - 0x8F
Device Configuration Regis-
ters
(Table 8)
Interrupt registers and global controls
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