XRT84L38_06 Datasheet, PDF (432/453 Pages) Exar Corporation – OCTAL T1/E1/J1 FRAMER

XRT84L38
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H)
BIT
NUMBER
BIT NAME
BIT TYPE
BIT DESCRIPTION
3
Receive End of
R/W 0 - The Receive End of Transfer interrupt is disabled.
Transfer Enable
1 - The Receive End of Transfer interrupt is enabled.
The table below shows configurations of the HDLC Controller Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H)
BIT
NUMBER
3
BIT NAME
HDLC Controller
Interrupt Enable
BIT TYPE
BIT DESCRIPTION
R/W 0 - Every interrupt generated by the HDLC Controller is disabled.
1 - Every interrupt generated by the HDLC Controller is enabled.
When these interrupt enable bits are set and the BOS message is received in the data link channel, the BOS
Processor changes the Receive Start of Transfer and Receive End of Transfer status bits of the Data Link
Status Register (DLSR). These two status indicators are valid until the Data Link Status Register is read.
Reading these register clears the associated interrupt if Reset Upon Read is selected in Interrupt Control
Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status
indicators.
The table below shows the Receive Start of Transfer and Receive End of Transfer status bits of the Data Link
Status Register.
DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H)
BIT
NUMBER
5
3
BIT NAME
Receive Start of
Transfer
Receive End of
Transfer
BIT TYPE
BIT DESCRIPTION
RUR /
WC
RUR /
WC
0 - There is no data link message in the data link channel.
1 - The HDLC Controller began to receive a data link message in the data
link channel.
0 - No data link message was present in the data link channel.
1 - The HDLC Controller finished receiving a data link message in the data
link channel.
The BOS Processor can also generate interrupts when either the BOS ABORT sequence (nine consecutive
ones) or the IDLE flag character (hexadecimal value of 0x7EH) is received in the data link channel to the
microprocessor. These are the Receive ABORT Sequence (RxABORT) interrupt and the Receive IDLE Flag
Sequence (RxIDLE) interrupt.
To enable these interrupts, the Receive ABORT Sequence Enable bit and the Receive IDLE Flag Sequence
Enable bit of the Data Link Interrupt Enable Register (DLIER) have to be set. In addition, the HDLC Controller
Interrupt Enable bit of the Block Interrupt Enable Register (BIER) needs to be one.
The table below shows configurations of the Receive ABORT Sequence Enable bit and the Receive IDLE Flag
Sequence Enable bit of the Data Link Interrupt Enable Register.
DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H)
BIT
NUMBER
1
BIT NAME
Receive ABORT
Sequence Enable
BIT TYPE
BIT DESCRIPTION
R/W 0 - The Receive ABORT Sequence interrupt is disabled.
1 - The Receive ABORT Sequence interrupt is enabled.
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