XRT84L38_06 Datasheet, PDF (367/453 Pages) Exar Corporation – OCTAL T1/E1/J1 FRAMER

XRT84L38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
The table below shows configurations of the Receive Red Alarm State Change Interrupt Enable bit of the Alarm
and Error Interrupt Enable Register (AEIER).
ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH,
0X03H)
BIT
NUMBER
BIT NAME
BIT TYPE
BIT DESCRIPTION
2
Receive Red Alarm R/W 0 - The Receive Red Alarm State Change interrupt is disabled. No Receive
State Change
Loss of Frame (RxLOF) interrupt will be generated upon detection of LOF
Interrupt Enable
condition.
1 - The Receive Red Alarm State Change interrupt is enabled. Receive
Loss of Frame (RxLOF) interrupt will be generated upon detection of LOF
condition.
The table below shows configurations of the Alarm and Error Interrupt Enable bit of the Block Interrupt Enable
Register.
BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H)
BIT
NUMBER
1
BIT NAME
BIT TYPE
BIT DESCRIPTION
Alarm and Error
Interrupt Enable
R/W 0 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is disabled.
1 - Every interrupt generated by the Alarm and Error Interrupt Status Reg-
ister (AEISR) is enabled.
When these interrupt enable bits are set and Red Alarm is present in the incoming DS1 frame, the XRT84L38
framer will declare Red Alarm by doing the following:
• Set the read-only Receive Red Alarm State bit of the Alarm and Error Status Register (AESR) to one
indicating there is Red Alarm detected in the incoming DS1 frame.
• Set the Receive Red Alarm State Change bit of the Alarm and Error Status Register to one indicating there is
a change in state of Red Alarm. This status indicator is valid until the Framer Interrupt Status Register is
read.
Reading this register clears the associated interrupt if Reset-Upon-Read is selected in Interrupt Control
Register (ICR). Otherwise, a write-to-clear operation by the microprocessor is required to reset these status
indicators.
The table below shows the Receive Red Alarm State Change status bits of the Alarm and Error Status
Register.
ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H)
BIT
NUMBER
BIT NAME
BIT TYPE
BIT DESCRIPTION
2
Receive Red Alarm RUR / 0 - There is no change of Red Alarm state in the incoming DS1 payload
State Change
WC data.
1 - There is change of Red Alarm state in the incoming DS1 payload data.
The Receive Red Alarm State bit of the Alarm and Error Status Register (AESR), on the other hand, is a read-
only bit indicating there is Red Alarm detected in the incoming DS1 frame.
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