XRT84L38_06 Datasheet, PDF (269/453 Pages) Exar Corporation – OCTAL T1/E1/J1 FRAMER

XRT84L38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
The Transmit Serial Clock (TxSerClk_n), Transmit Single-frame Synchronization Signal (TxSync_n) and
Transmit Multi-frame Synchronization Signal (TxMSync_n) can be either inputs or outputs depend on the
timing source of the Transmit section of the framer.
With the OSCCLK Driven Divided Clock or the Recovered Receive Line Clock being the timing source of the
transmit section, the Transmit Serial Clock (TxSerClk_n), Transmit Single-frame Synchronization Signal
(TxSync_n) and Transmit Multi-frame Synchronization Signal (TxMSync_n) are all outputs.
With the timing source of the transmit section being the Transmit Serial Input Clock, the Transmit Serial Clock
(TxSerClk_n), Transmit Single-frame Synchronization Signal (TxSync_n) and Transmit Multi-frame
Synchronization Signal (TxMSync_n) are all inputs.
The following table illustrates the input and output nature of these signals for different Transmit timing sources.
TRANSMIT TIMING SOURCE
Terminal Equipment Driven TxSerClk
OSCCLK Driven Divided Clock
Recovered Receive Line Clock
TXSERCLK_N
Input
Output
Output
TXSYNC_N
Input
Output
Output
TXMSYNC_N
Input
Output
Output
The Transmit Time-slot Indication Bits (TxTSb[4:0]_n) are multiplexed I/O pins. The functionality of these pins
is governed by the value of Transmit Fractional E1 Input Enable bit of the Transmit Interface Control Register
(TICR).
The following table illustrates the configurations of the Transmit Fractional E1 Input Enable bit.
TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H)
BIT
NUMBER
4
BIT NAME
Transmit
Fractional E1
Input Enable
BIT TYPE
BIT DESCRIPTION
R/W 0 - The Transmit Time-slot Indication bits (TxTSb[4:0] are outputting five-bit
binary values of Time-slot number (0-31) being accepted and processed by the
Transmit Payload Data Input Interface block of the framer.
The Transmit Time-slot Indicator Clock signal (TxTSClk_n) is a 256KHz clock
that pulses HIGH for one E1 bit period whenever the Transmit Payload Data
Input Interface block is accepting the LSB of each of the twenty-four time slots.
1 - The TxTSb[0]_n bit becomes the Transmit Fractional E1 Input signal
(TxFrTD_n) which carries Fractional E1 payload data into the framer.
The TxTSb[1]_n bit becomes the Transmit Signaling Data Input signal (TxSig_n)
which is used to insert robbed-bit signaling data into the outbound E1 frame.
The TxTSb[2]_n bit serially outputs all five-bit binary values of the Time Slot
number (0-31) being accepted and processed by the Transmit Payload Data
Input Interface block of the framer.
The TxTSb[3]_n bit becomes the Transmit Overhead Synchronization Pulse
(TxOHSync_n) which is used to output an Overhead Synchronization Pulse that
indicates the first bit of each E1multi-frame.
The TxTSClk_n will output gaped fractional E1 clock that can be used by Termi-
nal Equipment to clock out Fractional E1 payload data at rising edge of the clock.
Or,
The TxTSClk_n pin will be a clock enable signal to Transmit Fractional E1 Input
signal (TxFrTD_n) when the un-gaped Transmit Serail Input Clock (TxSerClk_n)
is used to clock in Fractional E1 Payload Data into the framer.
When configured to operate in normal condition (that is, when the Transmit Fractional E1 Input Enable bit is
equal to zero), these bits reflect the five-bit binary value of the Time Slot number (0-31) being accepted and
processed by the Transmit Payload Data Input Interface block of the framer. TxTSb[4] represents the MSB of
the binary value and TxTSb[0] represents the LSB.
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