XRD9824 Datasheet, PDF (4/32 Pages) Exar Corporation – 14-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control

XRD9824
ELECTRICAL CHARACTERISTICS
Test Conditions: AV_DD=DV_DD=5V, ADCCLK=6MHz, 50% Duty Cycle, T_A=25°C unless otherwise specified.
Symbol Parameter
Power Supplies
AV
DD
Analog Power Supply
DV_DD
Digital I/O Power Supply
I_DD
Supply Current
IDD_PD
Power Down Power Supply Current
ADC Specifications
RES
Resolution
F
s
DNL
Maximum Sampling Rate
Differential Non-Linearity
V_RT
V_RB
DV_REF
R
L
Top Reference Voltage
Bottom Reference Voltage
Differential Reference Voltage
(V_RT - V_RB)
Ladder Resistance
PGA & Offset DAC Specifications
PGARES
PGAG_MIN
PGAG
MAX
PGAGD
V_BLACK
DACRES
OFF
MIN
OFF_MAX
OFF
MIN
OFF_MAX
OFF∆
PGA Resolution
Minimum Gain
Maximum Gain
Gain Adjustment Step Size
Black Level Input Range
Offset DAC Resolution
Minimum Offset Adjustment
Maximum Offset Adjustment
Minimum Offset Adjustment
Maximum Offset Adjustment
Offset Adjustment Step Size
Min.
3.0
3.0
14
12
-3.0
3.50
0.3
300
6
0.950
9.5
-100
8
-250
+500
-450
+350
Typ. Max. Unit Conditions
3.3
5.5
V (Note 2)
3.3
5.5
V DV_DD < AV_DD
40
55
mA V_DD=5V
50
µA V_DD=5V
±1.5
AV_DD/1.3
AV_DD/10
0.67AV_DD
3.0
3.90
Bits
MSPS
LSB
V
V
V
600
780
Ω
1.0
10.0
0.14
-200
+600
-400
+400
3.14
1.050
10.50
500
-150
+700
-350
+450
Bits
V/V
V/V
V/V
mV DC Configuration
Bits
mV Mode 111, D5=0 (Note 1)
mV Mode 111, D5=0
mV Mode 111, D5=1 (Note 1)
mV Mode 111, D5=1
mV
Note 1: The additional ±100 mV of adjustment with respect to the black level input range is needed to compensate
for any additional offset introduced by the XRD9824 Buffer/PGA internally.
Note 2: It is not recommended to operate the part between 3.6V and 4.4V.
Rev. 2.00
4