XRD9824 Datasheet, PDF (29/32 Pages) Exar Corporation – 14-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control

XRD9824
Control Registers
Function
(Register
S2/S1/S0)
D7
D6
D5
D4
D3
D2
D1
D0
Power-up
State
(Note 1)
Red Gain
G5
G4
G3
(000)
(MSB)
G2
G1
G0
X
X
000000XX
(LSB)
Red Offset
O7
O6
O5
(001)
(MSB)
O4
O3
O2
O1
O0
01000000
(LSB)
Grn Gain
G5
G4
G3
(010)
(MSB)
G2
G1
G0
X
X
000000XX
(LSB)
Grn Offset
(011)
O7
O6
O5
(MSB)
O4
O3
O2
O1
O0
01000000
(LSB)
Blu Gain
(100)
G5
G4
G3
(MSB)
G2
G1
G0
X
X
000000XX
(LSB)
Blu Offset
(101)
O7
O6
O5
(MSB)
O4
O3
O2
O1
O0
01000000
(LSB)
Mode
(110)
POWER
DOWN
0: NORMAL
1:
POWER
DOWN
DIGITAL
V_RT
RESET
0: NO RESET 0: INTERNAL
1:RESET
(REGISTERS
ARE RESET TO
POWER-UP
STATES)
1: EXTERNAL
INPUT DC
REFERENCE
(V_DCREF)
0: INTERNAL
(V_DCREF=AGND)
1: EXTERNAL
(V_DCREF=V_DCEXT)
DC/AC
0: DC
1: AC
SIGNAL
POLARITY
SIGNAL
CONFIGURATION
00000000
0: Non-
Inverted
(CIS)
1: Inverted
(CCD/CIS)
00: Single-Channel
RED input/gain/offset
01: Single-Channel
RED input
RED/GRN/BLU
gain/offset cycle
pixel-by-pixel
10: Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
pixel-by-pixel
11: Triple-Channel
RED/GRN/BLU
input/gain/offset cycle
line-by-line
Mode
&Test
(111)
TEST5
OUTPUT
DISABLE
OFFSET
DAC
RANGE
INTERNAL CIS
REFERENCE
CIRCUIT
TEST4
TEST3
TEST2 TEST1 00000000
0:NORMAL
0:OUTPUTS
ENABLED
0:-200mV to
+600mV
0:NORMAL
0: TEST4 0: TEST3 0: TEST2 0:NORMAL
DISABLED DISABLED DISABLED
1:NOT USED
1:OUTPUTS
DISABLED
1:-400mV to
+400mV
1:REFERENCE
CIRCUIT
ENABLED
1: OUTPUT 1: OUTPUT
OF BUFFER OF PGA
TIED TO TIED TO
BLU
VDCEXT
1: INPUT
OF ADC
TIED TO
GRN
1: TEST1
ENABLED
Rev. 2.00
29