XRD9824 Datasheet, PDF (21/32 Pages) Exar Corporation – 14-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control

XRD9824
CCD
Channel N
ADCCLK
CLAMP
[5:0]
DB
[11:6]
AREA, LINEAR or B/W CCD -- AC Coupled
(CLAMP Enabled)
Pixel N-1
Pixel N
Pixel N+1
tckpd
tap
tap
tckhw tcklw
tclpw
tdv
tdv
N-8 N-8 N-7 N-7 _N-6
N-6
MSB _LSB MSB LSB MSB LSB
Figure 15. Timing Diagram for Figure 14
Triple Channel CCD Application
Figure 16, is a block diagram for pixel-by-pixel applica-
tions with triple channel CCDs. During the optically
shielded section of a pixel, CLAMP must go high to
store the black reference on each capacitor to the
input. The gain and offset is automatically rotated to
adjust for each channel input. The MSBs are available
on the output bus on the falling edge of ADCCLK. The
LSBs are available on the rising edge of ADCCLK.
Rev. 2.00
21