XR16M580IM48-0A Datasheet, PDF (4/56 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

XR16M580
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
PIN DESCRIPTIONS
REV. 1.0.0
Pin Description
NAME
32-QFN 48-TQFP 25-BGA
PIN#
PIN#
PIN#
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
17
26
A1
18
27
A0
19
28
D7
5
4
D6
4
3
D5
3
2
D4
1
47
D3
32
46
D2
31
45
D1
30
44
D0
29
43
IOR#
14
19
IOW#
12
16
(R/W#)
CS#
8
11
INT
20
30
(IRQ#)
A5
I _{Address lines [2:0]. These 3 address lines select the internal regis-}
A4
ters in UART channel during a data bus transaction.
B4
C3
I/O _{Data bus lines [7:0] (bidirectional).}
C2
E3
E1
D1
E2
D2
C1
B5
I _{When 16/68# pin is at logic 1, the Intel bus interface is selected and}
this input becomes read strobe (active low). The falling edge insti-
gates an internal read cycle and retrieves the data byte from an
internal register pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to read it on the ris-
ing edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input should be connected to VCC.
C5
I _{When 16/68# pin is at logic 1, it selects Intel bus interface and this}
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input becomes read (logic 1) and write (logic 0) signal.
D4
I _{This input is chip select (active low) to enable the device.}
A3
O _{When 16/68# pin is at logic 1 for Intel bus interface, this output}
(OD) become the active high device interrupt output. The output state is
defined by the user through the software setting of MCR[3]. INT is
set to the active mode when MCR[3] is set to a logic 1. INT is set to
the three state mode when MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes the active low device interrupt output (open drain). An
external pull-up resistor is required for proper operation.
MODEM OR SERIAL I/O INTERFACE
TX
7
8
D3
O _{UART Transmit Data or infrared encoder data. Standard transmit}
and receive interface is enabled when MCR[6] = 0. In this mode,
the TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
4