XR16M580IM48-0A Datasheet, PDF (31/56 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

REV. 1.0.0
XR16M580
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
TABLE 9: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
FCR BIT-7 FCR BIT-6 FCR BIT-5 FCR BIT-4
RECEIVE TRIGGER
LEVEL
TRANSMIT TRIGGER
LEVEL
COMPATIBILITY
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
1(default)
4
8
14
1(default)
4
8
14
16L580
4.6 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
0
0
1
1
BIT-0
0
1
0
1
WORD LENGTH
5 (default)
6
7
8
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
BIT-2
0
1
1
WORD
LENGTH
5,6,7,8
5
6,7,8
STOP BIT LENGTH
(BIT TIME(S))
1 (default)
1-1/2
2
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 10 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
31