XR20V2172 Datasheet, PDF (34/51 Pages) Exar Corporation – TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER

XR20V2172
PRELIMINARY
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
REV. P1.0.1
4.17 GPIO Interrupt Enable Register (IOIntEna) - Read/Write
This register enables the interrupt for the GPIO pins. The interrupts for GPIO[7:4] are only enabled if
IOControl[1] = 0. If IOControl[0] = 1 (GPIO pins are selected as modem IOs) , then IOIntEna[7:4] will have no
effect on GPIO[7:4].
• Logic 0 = a change in the input pin will not generate an interrupt
• Logic 1 = a change in the input will generate an interrupt
4.18 GPIO Control Register (IOControl) - Read/Write
IOControl bits 2-1 should be set to a logic 1 to behave like modem IOs that can be controlled and monitored via
the MCR and MSR registers. If not, by default, they are GPIOs controlled by IODir, IOState and IOIntEna.
IOControl[7:4]: Reserved
IOControl[3]: UART Software Reset
Writing a logic 1 to this bit will reset the device. Once the device is reset, this bit will automatically be set to a
logic 0.
IOControl[2]: GPIO[3:0] or Modem IO Select (CH B)
This bit controls whether GPIO[3:0] behave as GPIO pins or as modem IO pins (RIB#, CDB#, DTRB#, DSRB#)
• Logic 0 = GPIO[3:0] behave as GPIO pins
• Logic 1 = GPIO[3:0] behave as RIB#, CDB#, DTRB#, DSRB#. Note: DTRB# will also need to be set as an
output via IODir bit-1.
IOControl[1]: GPIO[7:4] or Modem IO Select (CH A)
This bit controls whether GPIO[7:4] behave as GPIO pins or as modem IO pins (RIA#, CDA#, DTRA#, DSRA#)
• Logic 0 = GPIO[7:4] behave as GPIO pins
• Logic 1 = GPIO[7:4] behave as RIA#, CDA#, DTRA#, DSRA#. Note: DTRA# will also need to be set as an
output via IODir bit-5.
IOControl[0]: IO Latch
This bit enable/disable GPIO inputs latching.
• Logic 0 = GPIO input values are not latched. A change in any GPIO input generates an interrupt. A read of
the IOState register clears the interrupt. If the input goes back to its initial logic state before the input register
is read, then the interrupt is cleared.
• Logic 1 = GPIO input values are latched. A change in the GPIO input generates an interrupt and the input
logic value is loaded in the bit of the corresponding input state register (IOState). A read of the IOState
register clears the interrupt. If the input pin goes back to its initial logic state before the interrupt register is
read, then the interrupt is not cleared and the corresponding bit of the IOState register keeps the logic value
that generated the interrupt.
4.19 Extra Features Control Register (EFCR) - Read/Write
EFCR[7:3]: Reserved
These bits are reserved and should be left at "0000".
EFCR[2]: Transmitter Disable
UART does not send serial data out on the TX output pin, but the TX FIFO will continue to receive data from
CPU until full. Any data in the TSR will be sent out before the trasnmitter goes into disable state.
• Logic 0 = Transmitter is enabled
• Logic 1 = Transmitter is disabled
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