XR20V2172 Datasheet, PDF (22/51 Pages) Exar Corporation – TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER

XR20V2172
PRELIMINARY
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
.
REV. P1.0.1
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDR
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0x00 RHR
RD Bit-7
Bit-6
Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0x00 THR WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0x01
IER RD/WR 0/
0/
0/
0/
Modem RX Line TX RX Data
CTS Int. RTS Int. Xoff Int.
Enable Enable Enable
Sleep
Mode
Enable
Stat. Int. Stat. Int. Empty Int.
Enable Enable Int Enable
Enable
0x02 ISR
RD FIFOs FIFOs
0/
Enabled Enabled
INT
Source
Bit-5
0/
INT
Source
Bit-4
INT
INT
INT
INT
Source Source Source Source
Bit-3 Bit-2 Bit-1 Bit-0
LCR[7]=0
0x02 FCR
WR RXFIFO RXFIFO 0/
0/
DMA TX FIFO RX FIFOs
Trigger Trigger
TXFIFO TX FIFO
Trigger Trigger
Mode
Enable
Reset
FIFO Enable
Reset
0x03
0x04
0x05
LCR
MCR
LSR
RD/WR Divisor Set TX Set Par- Even Par- Parity
Enable Break
ity
ity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
RD/WR 0/
Clock
Pres-
caler
Select
0/
0/
Internal OP2#/
0/
RTS# DTR#
XonAny
Lopback
Enable
INT Out-
Output
put ^Enable Control
Enable ^TCR
and TLR
Output
Control
LCR≠0xBF
RD RX FIFO THR &
Global TSR
Error Empty
THR RX Break RX
RX
Empty
Framing Parity
Error Error
RX
Over-
run
Error
RX Data
Ready
0x06 MSR
RD CD# RI# Input DSR# CTS#
Input
Input
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
See Table 12
0x07 SPR RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0 See Table 13
0x06
TCR RD/WR Resume Resume Resume Resume
Bit-3 Bit-2 Bit-1
Bit-0
Halt
Bit-3
Halt
Bit-2
Halt
Bit-1
Halt _{See Table 12}
Bit-0
0x07
TLR
RD/WR RX Trig RX Trig RX Trig
Bit-3 Bit-2 Bit-1
RX Trig
Bit-0
TX Trig
Bit-3
TX Trig
Bit-2
TX Trig
Bit-1
TX Trig
Bit-0
See Table 13
0x08 TXLVL RD/WR 0
Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0x09 RXLVL RD/WR 0
Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
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