XR17V354IB-E4-EVB Datasheet, PDF (31/67 Pages) Exar Corporation – HIGH PERFORMANCE QUAD PCI-EXPRESS UART

REV. 1.0.4
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
Channel 0 to 3 Receive Data in 32-bit alignment through the Configuration Register Address
0x0100, 0x0500, 0x0900 and 0x0D00
Receive Data Byte n+3
Receive Data Byte n+2
Receive Data Byte n+1
Receive Data Byte n+0
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
PCI Bus
Data Bit-31
PCI Bus
Data Bit-0
2.1.2 Special Rx FIFO Data Unloading at locations 0x0200, 0x0600, 0x0A00 and 0x0E00
The XR17V354 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x0200 (channel 0), 0x0600 (channel 1), 0x0A00 (channel 2) and 0x0E00 (channel 3).
The Status and Data bytes must be read in 16 or 32 bits format to maintain data integrity. The following tables
show this clearly.
READ RX FIFO,
WITH LSR ERRORS
Read n+0 to n+1
Read n+2 to n+3
Etc
BYTE 3
FIFO Data n+1
FIFO Data n+3
BYTE 2
LSR n+1
LSR n+3
BYTE 1
FIFO Data n+0
FIFO Data n+2
BYTE 0
LSR n+0
LSR n+2
Channel 0 to 3 Receive Data with Line Status Register in 32-bit alignment through the Configuration
Register Address 0x0200, 0x0600, 0x0A00 and 0x0E00
Receive Data Byte n+1
Line Status Register n+1
Receive Data Byte n+0
Line Status Register n+0
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
PCI Bus
Data Bit-31
PCI Bus
Data Bit-0
2.1.3 Tx FIFO Data Loading at locations 0x100, 0x500, 0x900 and 0xD00
The TX FIFO data can be loaded 32 bits (4 bytes) at a time at memory locations 0x0100 (channel 0), 0x0500
(channel 1), 0x0900 (channel 2) and 0x0D00 (channel 3).
WRITE TX FIFO
Write n+0 to n+3
Write n+4 to n+7
Etc.
BYTE 3
FIFO Data n+3
FIFO Data n+7
BYTE 2
FIFO Data n+2
FIFO Data n+6
BYTE 1
FIFO Data n+1
FIFO Data n+5
BYTE 0
FIFO Data n+0
FIFO Data n+4
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