XR17V354IB-E4-EVB Datasheet, PDF (16/67 Pages) Exar Corporation – HIGH PERFORMANCE QUAD PCI-EXPRESS UART

XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
REV. 1.0.4
Table 3 shows the Target Addresses available for programming into bits 7:0 of the 16-bit address word. All
other Target Addresses are reserved and must not be used.
TABLE 3: TARGET ADDRESS FOR EEPROM VALUES
TARGET ADDRESS
DATA
EXAR DEFAULT
0x00
Vendor ID
0x13A8
0x01
Device ID
0x0354 - No slave
0x4354 - XR17V354 slave present
0x8354 - XR17V358 slave present
0x02
Class Code [7:0]
lower 8-bits are reserved
0x0200
0x03
Class Code [23:8]
0x0700
0x04
Subsystem Vendor ID
0x0000
0x05
Subsystem ID
0x0000
The second 16-bit word of the address/data pair is the data. The default values are shown in Table 3. The
address/data pairs can be in any order. Only the contents which need to be changed from the Exar defaults
need to be included in the EEPROM.
1.3 Device Internal Register Sets
The Device Configuration Registers and the four individual UART Configuration Registers of the V354
occupy 4K of PCI bus memory address space. These addresses are offset onto the basic memory address, a
value loaded into the Memory Base Address Register (BAR) in the PCI local bus configuration register set. The
UART Configuration Registers are mapped into 4 address blocks where each UART channel occupies 1024
bytes memory space for its own registers that include the 16550 compatible registers. The Device
Configuration Registers are accessible from all UART channels. However, not all bits can be controlled by all
channels. The UART channel can only control the 8XMODE, 4XMODE, RESET and SLEEP register bits that
apply to that particular channel. For example, this prevents channel 0 from accidentally resetting channel 1.
All these registers can be accessed in 8, 16, 24 or 32 bits width depending on the starting address given by the
host at the beginning of the bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32
bits format in special locations given in the Table 4 below. Every time a read or write operation is made to the
transmit or receive register, its FIFO data pointer is automatically bumped to the next sequential data location
either in byte, word or DWORD. One special case applies to the receive data unloading when reading the
receive data together with its LSR register content. The host must read them in 16 or 32 bits format in order to
maintain integrity of the data byte with its associated error flags. These special registers are further discussed
in “Section 2.1, FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT” on page 30.
16