XR16M681 Datasheet, PDF (3/51 Pages) Exar Corporation – 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE

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PIN DESCRIPTIONS
XR16M681
1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE
Pin Description
NAME
24-QFN
PIN#
32-QFN
PIN#
25-BGA
PIN#
TYPE
DESCRIPTION
DATA BUS INTERFACE
AD0
20
29
AD1
21
30
AD2
22
31
AD3
23
32
AD4
24
1
AD5
1
3
AD6
2
4
AD7
3
5
IOR#
12
14
IOW#
10
12
CS#
6
8
LLA#
14
19
INT
15
20
C1
I/O _{Multiplexed Address/Data lines [7:0]. The register address is}
D2
latched on the rising edge of the LLA#. After the LLA# signal goes
E2
high, the UART enters the data phase where the data is placed on
D1
these lines.
E1
B2
E3
C2
A5
I _{Read strobe (active low). The falling edge instigates an internal}
read cycle and retrieves the data byte from an internal register
pointed by the latched address. The UART places the data byte on
the data bus to allow the host processor to read it on the rising
edge.
E5
I _{Write strobe (active low). The falling edge instigates the internal}
write cycle and the rising edge transfers the data byte on the data
bus to an internal register pointed by the latched address.
D3
I _{Chip select (active low). The falling edge starts the access to the}
UART. A read or write is determined by the IOR# and IOW# sig-
nals.
A4
I _{Latch Lower Address (active low). The register address is latched}
on the rising edge of the LLA# signal. After the LLA# goes high, the
device enters the data phase where the data is placed on the
AD[7:0] lines.
B4
O _{Interrupt output (active high). The output state is defined by the}
user through the software setting of MCR[3]. INT is set to the active
mode when MCR[3] is set to a logic 1. INT is set to the three state
mode when MCR[3] is set to a logic 0. See MCR[3].
MODEM OR SERIAL I/O INTERFACE
TX
5
7
E4
RX
4
6
C3
RTS#
16
21
A3
O _{UART Transmit Data or infrared encoder data. Standard transmit}
and receive interface is enabled when MCR[6] = 0. In this mode,
the TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
I _{UART Receive Data or infrared receive data. Normal receive data}
input must idle at logic 1 condition. The infrared receiver idles at
logic 0. This input should be connected to VCC when not used.
O _{UART Request-to-Send (active low) or general purpose output.}
This output must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1] and IER[6]. This pin can also be used as the
Auto RS-485 Half-duplex Direction control output, see FCTR[3] and
EMSR[3].
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