XR16M681 Datasheet, PDF (12/51 Pages) Exar Corporation – 1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE

XR16M681
1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE
FIGURE 7. BAUD RATE GENERATOR
REV. 1.0.1
XTAL1
XTAL2
Crystal
Osc /
Buffer
Prescaler
Divide by 1
DLD[7]=0
MCR Bit -7= 0
(default)
DLL
DLM
DLD[5:0]
Prescaler
Divide by 4
MCR Bit -7=1
DLD[7]=1
DLL
DLM
DLD[5:0]
0
1
DLD[6]
16X or 8X or 4X
Sampling Rate Clock
to Transmitter
16X or 8X or 4X
Sampling Rate Clock
to Receiver
TABLE 3: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
Required
Output Data
Rate
400
2400
4800
9600
10000
19200
25000
28800
38400
50000
57600
75000
100000
115200
153600
200000
225000
230400
250000
300000
400000
460800
500000
750000
921600
1000000
DIVISOR FOR 16x
Clock
(Decimal)
3750
625
312.5
156.25
150
78.125
60
52.0833
39.0625
30
26.0417
20
15
13.0208
9.7656
7.5
6.6667
6.5104
6
5
3.75
3.2552
3
2
1.6276
1.5
DIVISOR
OBTAINABLE IN
M681
3750
625
312 8/16
156 4/16
150
78 2/16
60
52 1/16
39 1/16
30
26 1/16
20
15
13
9 12/16
7 8/16
6 11/16
6 8/16
6
5
3 12/16
3 4/16
3
2
1 10/16
1 8/16
DLM PROGRAM
VALUE (HEX)
E
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DLL PROGRAM DLD PROGRAM DATA ERROR
VALUE (HEX) VALUE (HEX) RATE (%)
A6
0
0
71
0
0
38
8
0
9C
4
0
96
0
0
4E
2
0
3C
0
0
34
1
0.04
27
1
0
1E
0
0
1A
1
0.08
14
0
0
F
0
0
D
0
0.16
9
C
0.16
7
8
0
6
B
0.31
6
8
0.16
6
0
0
5
0
0
3
C
0
3
4
0.16
3
0
0
2
0
0
1
A
0.16
1
8
0
12