XRT94L33_3 Datasheet, PDF (292/801 Pages) Exar Corporation – -CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER - SONET REGISTERS

XRT94L33
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Rev222...000...000
Table 191: Redundant Receive STS-3 Transport – Receive SF CLEAR Threshold – Byte 0 (Address
Location= 0x173B)
BIT 7
R/W
1
BIT 6
R/W
1
BIT 5
R/W
1
BIT 4
BIT 3
SF_CLEAR_THRESHOLD[7:0]
R/W
R/W
1
1
BIT 2
R/W
1
BIT 1
R/W
1
BIT 0
R/W
1
BIT NUMBER
7-0
NAME
SF_CLEAR_THRESHOLD
[7:0]
TYPE
R/W
DESCRIPTION
SF_CLEAR_THRESHOLD – LSB:
These READ/WRITE bits, along the contents of the
“Redundant Receive STS-3 Transport – SF CLEAR Threshold
– Byte 1” registers permit the user to specify the upper limit for
the number of B2 bit errors that will cause the Redundant
Receive STS-3 TOH Processor block to clear the SF (Signal
Failure) defect condition.
When the Redundant Receive STS-3 TOH Processor block is
checking the incoming STS-3 signal in order to determine if it
should clear the SF defect condition, it will accumulate B2 byte
errors throughout the “SF Defect Clearance Monitoring
Period”. If the number of accumulated B2 byte errors is less
than that programmed into this and the “Redundant Receive
STS-3 Transport SF CLEAR Threshold – Byte 1” register, then
the Redundant Receive STS-3 TOH Processor block will clear
the SF defect condition.
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