XRP7725 Datasheet, PDF (28/34 Pages) Exar Corporation – Power Management System

XRP7725
Intel Node Manager Compatible Programmable
Power Management System
The host should time its reading frequency to
match the sample window size. A GPIO/PSIO
can be configured in PA 5.1 to indicate to the
host each time a new accumulated sum has
been latched.
The internal counter can be reinitialized by
reading from the following I²C command:
0x70 (VIL_ACC_INIT) – Accumulator Initialization
These I²C commands follow
command structure as the
described in ANP-38.
the same
commands
Once the host reads the accumulated sum, it
will need to do some post data processing in
order to get an average load current.
First, the host has to divide the read sum by a
number of samples to obtain an average V_IL
register value.
Secondly, the average V_IL register value
needs to be translated into a load current.
Translating average V_IL register value
into a load current
To adjust for the gain and offset of the sense
circuit the average V_IL register value needs to
be converted to V_IL. That can be done with
the following equation:
DEC(R _ Value)* 0.01
V_{GL _ RTN} − V_LX = V_IL =
IFE _ Gain
− 0.04
The IO will be asserted after all samples have
been taken and held while the accumulated
values are being latched.
Reading of the accumulated sum is done
using following I²C commands:
0x71 (VIL_ACC_READ_CH1) – CH1 Accumulator
0x72 (VIL_ACC_READ_CH2) – CH2 Accumulator
0x73 (VIL_ACC_READ_CH3) – CH3 Accumulator
0x74 (VIL_ACC_READ_CH4) – CH4 Accumulator
Equation 1
where IFE_Gain is a gain setting of the sense
circuit. The IFE_Gain equals to 8 if Gain 8 of
the sense circuit is enabled, else IFE_Gain is
4.
PA 5.1 sets the gain based on R_DSON, I_OUTMAX
values entered, and current sense ADC range.
The IFE_Gain value can be obtained by
reading register 0xD016 via the PA 5.1 Peek
Poke function. This is a four bit register with
following bit description:
Bit 0 – IFE_Gain 8 setting for channel 1
Bit 1 – IFE_Gain 8 setting for channel 2
Bit 2 – IFE_Gain 8 setting for channel 3
Bit 3 – IFE_Gain 8 setting for channel 4
Value 1 indicates gain 8 setting while value 0
indicates gain 4.
Reading this register from customer software
requires implementation of I²C register read
command structure described in ANP-39.
© 2014 Exar Corporation
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Rev. 1.0.0