XRP7725 Datasheet, PDF (25/34 Pages) Exar Corporation – Power Management System

XRP7725
Intel Node Manager Compatible Programmable
Power Management System
When the controller switches over to the
V5EXT rail, the V5EXT_RISE interrupt is
generated to inform the host. Similarly, when
the controller switches out, the V5EXT_FALL
interrupt gets generated.
EXTERNAL CLOCK SYNCHRONIZATION
XRP7725 can be run off an external clock
available in the system or another XRP7725.
The external clock must be in the ranges of
10.9MHz to 14.7MHz or 21.8MHz to 29.6MHz.
Locking to the external clock is done through
an internal Phase Lock Loop (PLL) which
requires an external loop capacitor of 2.2nF to
be connected between the CPLL pin and
AGND.
In applications where this functionality is not
desired, the CPLL capacitor is not necessary
and can be omitted, and the pin shall be left
floating. In addition, the user needs to make
sure the function gets disabled through
register settings.
The external clock must be routed to GPIO0.
The GPIO0 setting must reflect the range of
the external clock applied to it: Sys_Clock/8
corresponds to the range of 10.9MHz to
14.7MHz while Sys_Clock/4 setting
corresponds to the range of 21.8Mhz to
29.6MHz.
The functionality is enabled in PA 5.1 by
selecting External Clock-in function under
GPIO0.
For more details on how to monitor PLL lock
in-out, please contact Exar or your local Exar
representative.
CLOCK OUT
XRP7725 can supply clock out to be used by
another XRP7725 controller. The clock is
routed out through GPIO1 and can be set to
system clock divided by 8 (Sys_Clock/8) or
system clock divided by 4 (Sys_Clock/4)
frequencies.
The functionality is enabled in PA 5.1 by
selecting External Clock-Out function under
GPIO1.
CHANNEL CONTROL
Channels including LDO3.3 can be controlled
independently by any GPIO/PSIO or I²C
command. Channels will start-up or shut-
down following transitions of signals applied
to GPIO/PSIOs set to control the channels.
The control can always be overridden with an
I²C command.
Regardless of whether the channels are
controlled independently or are in a group,
the ramp rates will be followed as specified
(see the Power Sequencing section).
Regulated voltages and voltage drops across
the synchronous FET on each switching
channel can be read back using I²C
commands. The regulated voltage read back
resolution is 15mV, 30mV and 60mV per LSB
depending on the target voltage range. The
voltage drop across synchronous FET read
back resolution is 1.25mV and 2.5mV per LSB
depending on the range.
Through an I²C command the host can check
the status of the channels; whether they are
in regulation or at fault.
Regulated voltages can be dynamically
changed on switching channels using I²C
© 2014 Exar Corporation
25/34
Rev. 1.0.0