XRP7725 Datasheet, PDF (18/34 Pages) Exar Corporation – Power Management System

CLOCKS AND TIMING
÷4/÷8
Reg
XRP7725
Intel Node Manager Compatible Programmable
Power Management System
Clock
Divider
Ext Clock Output
GPIO1
Ext Clock Input
GPIO0
PLL
x4/x8
Reg
System Clock
Frequency
Set Reg
DPWM
Base Frequency
2x
4x
Sequencer
Freg Mult Reg
SEL
CH1 Timing
To Channels 2→4
Figure 18: XRP7725 Timing Block Diagram
Figure 18 shows a simplified block diagram of
the XRP7725 timing. Again, please note that
the function blocks and signal names used are
chosen for ease of understanding and do not
necessarily reflect the actual design.
The system timing is generated by a 103MHz
internal system clock (Sys_Clk). There are
two ways that the 103MHz system clock can
be generated. These include an internal
oscillator and a Phase Locked Loop (PLL) that
is synchronized to an external clock input.
The basic timing architecture is to divide the
Sys_Clk down to create a fundamental
switching frequency (Fsw_Fund) for all the
output channels that is settable from 105kHz
to 306kHz. The switching frequency for a
channel (Fsw_CHx) can then be selected as 1
time, 2 times or 4 times the fundamental
switching frequency.
channel then has its own frequency multiplier
register that is used to select its final output
switching frequency.
Table 1 shows the available channel switching
frequencies for the XRP7725 device. In
practice the PowerArchitect™ 5.1 (PA 5.1)
design tool handles all the details and the
user only has to enter the fundamental
switching frequency and the 1x, 2x, 4x
frequency multiplier for each channel.
If an external clock is used, the frequencies in
this table will shift accordingly.
To set the base frequency for the output
channels, an “Fsw_Set” value representing
the base frequency shown in Table 1, is
entered into the switching frequency
configuration register. Note that Fsw_Set
value is basically equal to the Sys_Clk divided
by the base frequency. The system timing is
then created by dividing down Sys_Clk to
produce a base frequency clock, 2X and 4X
times the base frequency clocks, and
sequencing timing to position the output
channels relative to each other. Each output
© 2014 Exar Corporation
18/34
Rev. 1.0.0