XRT73LC00A Datasheet, PDF (23/53 Pages) Exar Corporation – E3/DS3/STS-1 LINE INTERFACE UNIT

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PRELIMINARY
XRT73LC00A
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.0
SYSTEM DESCRIPTION
A functional block diagram of the XRT73LC00A E3/
DS3/STS-1 Transceiver IC (see Figure 1) shows that
the device contains three distinct sections:
• The Transmit Section
• The Receive Section
• The Microprocessor Serial Interface
THE TRANSMIT SECTION
The Transmit Section accepts TTL/CMOS level sig-
nals from the Terminal Equipment in either a Single-
Rail or Dual-Rail format. The Transmit Section then
takes this data and does the following:
• Encodes the data into the B3ZS format if the DS3
or SONET STS-1 Modes have been selected or
into the HDB3 format if the E3 Mode has been
selected.
• Converts the CMOS level B3ZS or HDB3 encoded
data into pulses with shapes that are compliant with
the various industry standard pulse template
requirements.
• Drives these pulses onto the line via the TTIP and
TRING output pins across a 1:1 Transformer.
NOTE: The Transmit Section drives a "1" (or a Mark) on the
line by driving either a positive or negative polarity pulse
across the 1:1 Transformer within a given bit period. The
Transmit Section drives a "0" (or a Space) onto the line by
driving no pulse onto the line.
THE RECEIVE SECTION
The Receive Section receives a bipolar signal from
the line either via a 1:1 Transformer or a 0.01mF Ca-
pacitor. As the Receive Section receives this line sig-
nal it does the following:
• Adjusts the signal level through an AGC circuit.
• Optionally equalizes this signal for cable loss.
• Attempts to quantify a bit-interval within the line sig-
nal as either a “1”, “-1” or a “0” by slicing this data.
This sliced data is used by the Clock Recovery PLL
to recover the timing element within the line signal.
• The sliced data is routed to the HDB3/B3ZS
Decoder, during which the original data content as
transmitted by the Remote Terminal Equipment is
restored to its original content.
• Outputs the recovered clock and data to the Local
Terminal Equipment in the form of CMOS level sig-
nals via the RPOS, RNEG, RCLK1 and RCLK2 out-
put pins.
THE MICROPROCESSOR SERIAL INTERFACE
The XRT73LC00A can be configured to operate in ei-
ther the Hardware Mode or the HOST Mode.
The Hardware Mode
Connect the HOST/HW input pin (pin 18) to GND to
configure the XRT73LC00A to operate in the Hard-
ware Mode.
When the XRT73LC00A is operating in the Hardware
Mode, the following is true:
1. The Microprocessor Serial Interface block is
disabled.
2. The XRT73LC00A is configured via input pin set-
tings.
Each of the pins associated with the Microprocessor
Serial Interface takes on their alternative role as de-
fined in Table 1.
3. All of the remaining input pins become active.
TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE PINS WHEN THE XRT73LC00A IS OPERATING IN THE
HARDWARE MODE
PIN #
PIN NAME
FUNCTION WHILE IN THE HARDWARE MODE
11
REGRESET/(RCLK2INV)
RCLK2INV
19
SDI/(LOSMUTEN)
LOSMUTEN
20
SDO/(LCV)
LCV
21
SCLK/(ENDECDIS)
ENDECDIS
22
CS/(DR/SR)
DR/SR
30
LCV/(RCLK2)
RCLK2
20