XR16M2751_07 Datasheet, PDF (23/53 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO

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XR16M2751
1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
IER RD/WR 0/
0/
0/
0/
Modem RX Line TX
RX
Stat. Int. Stat. Empty Data ^LCR[7]=0
CTS Int. RTS Int. Xoff Int. Sleep _{Enable Int.}
Int
Int.
Enable Enable Enable Mode
Enable Enable Enable
Enable
010
010
ISR
FCR
RD FIFOs FIFOs
0/
0/
INT
INT INT INT
Enabled Enabled
INT
INT
Source Source
Source Source Source Source
Bit-3 Bit-2 Bit-1 Bit-0
Bit-5 Bit-4
WR RXFIFO RXFIFO 0/
LCR ≠ 0xBF
0/
DMA
TX
RX FIFOs
Trigger Trigger
TXFIFO TXFIFO
Trigger Trigger
Mode
Enable
FIFO FIFO Enable
Reset Reset
011
100
LCR RD/WR Divisor Set TX Set Par- Even
Enable Break
ity
Parity
Parity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
MCR RD/WR
0/
BRG
Pres-
caler
0/
IR Mode
ENable
0/
XonAny
Internal OP2#/INT Rsrvd RTS# DTR#
Lopback Output _(OP1#) Output Output
Enable Enable
Control Control
101
110
111
111
LSR RD RX FIFO THR & THR
Global TSR Empty
Error Empty
MSR RD
CD#
Input
SPR RD/WR Bit-7
RI#
Input
Bit-6
DSR#
Input
Bit-5
EMSR WR
16X
Sam-
pling
Rate
Mode
LSR
Error
Inter-
rupt.
Imd/Dly#
Auto
RTS
Hyst.
bit-3
RX RX Fram- RX
Break ing Error Parity
Error
RX
Over-
run
Error
RX ^{LCR ≠ 0xBF}
Data
Ready
CTS#
Input
Delta
CD#
Delta Delta Delta
RI# DSR# CTS#
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0 LCR ≠ 0xBF
FCTR[6]=0
Auto
RTS
Hyst.
bit-2
Auto
RS485
Output
Inversion
Rsrvd
Rx/Tx
FIFO
Count
Rx/Tx
FIFO
Count
LCR ≠ 0xBF
FCTR[6]=1
1 1 1 FLVL RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
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