XR16V2650_07 Datasheet, PDF (22/47 Pages) Exar Corporation – HIGH PERFORMANCE DUART WITH 32-BYTE FIFO

XR16V2650
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
.
REV. 1.0.2
TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
IER RD/WR 0/
0/
0/
0/
Modem RX Line TX
RX _LCR[7]=0
Stat. Int. Stat. Empty Data
CTS Int. RTS Int. Xoff Int. Sleep _{Enable Int.}
Int
Int.
Enable Enable Enable Mode
Enable
Enable Enable Enable
010
010
ISR
FCR
RD FIFOs FIFOs
0/
0/
INT
INT INT INT
Enabled Enabled
Source Source Source Source
RTS/ Xoff/Xon _Bit-3
Bit-2 Bit-1 Bit-0
CTS INT special
Status INT
LCR ≠ 0xBF
WR
RX
RX
0/
0/
DMA
TX
RX FIFOs
FIFO
Trigger
FIFO
Trigger
TX FIFO
Trigger
TX FIFO
Trigger
Mode
Enable
FIFO FIFO Enable
Reset Reset
011
LCR RD/WR Divisor Set TX Set
Enable Break _Parity
Even
Parity
Parity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
100
MCR RD/WR
0/
BRG
Pres-
caler
0/
IR Mode
Enable
0/
XonAny
Internal OP2#/INT (OP1#) RTS# DTR#
Loop-
back
Enable
Output
Output Output
Enable ^{IR Input} Control Control
Invert
1 0 1 LSR RD RX FIFO THR & THR
RX RX Fram- RX
RX
RX
Global TSR Empty Break ing Error Parity Over- Data LCR ≠ 0xBF
Error Empty
Error run Ready
Error
1 1 0 MSR RD
CD# RI# Input DSR# CTS#
Input
Input Input
Delta
CD#
Delta Delta Delta
RI# DSR# CTS#
1 1 1 SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
000
001
010
DLL RD/WR
DLM RD/WR
DLD RD/WR
Bit-7
Bit-7
0
0 0 0 DREV RD
0 0 1 DVID RD
Bit-7
0
Baud Rate Generator Divisor
Bit-6 Bit-5 Bit-4
Bit-3
Bit-6 Bit-5 Bit-4
Bit-3
0 4X Mode 8X Mode Bit-3
Bit-6
0
Bit-5
0
Bit-4
0
Bit-3
0
Bit-2
Bit-2
Bit-2
Bit-2
1
Bit-1
Bit-1
Bit-1
Bit-1
1
Bit-0 ^LCR[7]=1
LCR ≠ 0xBF
Bit-0
Bit-0
LCR[7]=1
LCR ≠ 0xBF
EFR[4] = 1
Bit-0
0
LCR[7]=1
LCR ≠ 0xBF
DLL=0x00
DLM=0x00
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