XRD9818 Datasheet, PDF (21/28 Pages) Exar Corporation – 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR

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XRD9818
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
5.0 SERIAL PORT INTERFACE
The XRD9818 can be configured through a three pin interface (LOAD, SDI, and SCLK) with the serial port write
timing shown below. Each write will include 4 bits of address, two dummy bits and 10 bits of data. To insure
a valid write operation, the serial port control must detect minimum of 16 rising SCLK edges. Upon a valid
write the XRD9818 will latch the last 16 bits of data presented at the rising edge of LOAD. The register
address will be decoded and the 10bits of data will over write the contents of the addressed register. The
LOAD setup time "Tls" can be indefinitely long.
FIGURE 13. SERIAL PORT WRITE TIMING
LOAD
SCLK
SDI
Tls
Tsclk
Tlpw
Tds
Tlh
Tdh
msb
lsb
msb
lsb
E1 A3 A2 A1 A0 E0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D
D
u ^{Register Address} u
m
m
m
m
y
y
Write Register Data
LOAD is used to gate the SCLK input into the XRD9818. In order to eliminate any unintended high speed
clocks into the part it is recommended that the LOAD signal only be active during the write operation.
FIGURE 14. LOAD GATING OF SCLK
LOAD
SCLK
SCLK
(internal)
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