XRD9818 Datasheet, PDF (16/28 Pages) Exar Corporation – 3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR

XRD9818
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
xr
4.0 CIRCUIT OPERATION
4.1 Analog Inputs
4.1.1 Sampling
The XRD9818’s analog front end (AFE) uses a switched capacitor network to achieve a correlated double
sample (CDS) of the input in CCD mode or a sample and hold (S/H) of the input in CIS mode. Figure 3 shows
the 9818’s AFE (CDS/SH + PGA) which samples and gains the input signal. Figure 4 shows the external and
internal timing requirements to achieve a correlated double sample and gain of a CCD input signal.
FIGURE 3. XRD9818 INPUT CIRCUITRY
φ_B
SW4
Input
φ_R
SW2
C1
SW1 φ_CL
C2
Reference
SW3 _φR
C3
φ_V
SW6
C5
C6
SW7
C4
φ_V
SW5
φ_B
φ_V
SW8
C7
C8
SW9
φ_V
to ADC
C1 = C2 = 7.5pf
C3 = C4 = 7.5pf or 11pf
C5 = C6 = 1.5pf or 7.89pf
C7 = C8 = 1pf
In addition to sampling and gaining the CCD signal the 9818 input is designed to reject the reset pulse noise
present also. The XRD9818 can withstand reset pulses up to 1.5V or more depending upon the input
conditions. The timing signal φ_R controls SW2 and SW3 is generated internally by the XRD9818. SW2 and
SW3 open after a short delay following the sampling edge of VSAMP and close at the leading edge of BSAMP.
FIGURE 4. INTERNAL AFE SAMPLE TIMING (EX. 3CH CCD MODE)
CCD_IN
ADCLK _byte
ADCLK _nibble
BSAMP
VSAMP
φ_R
φ_B
φ_V
Note : φ_V = ADCLK VSAMP
The XRD9818 utilizes a differential input and signal path which samples the CCD reference level on capacitors
C1 and C2. When φ_B goes high, SW4 and SW5 close storing the CCD reference level on C1 and C2. When
φ_B goes low a fixed gain is applied to the input signal as it tracks the video input. When φ_V goes high the video
content is applied to capacitors C5 and C6. The final video level is stored on C5 and C6 when φ_V goes low.
The video content is then amplified again and sampled by the ADC at the proper time
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