XR77103 Datasheet, PDF (20/28 Pages) Exar Corporation – 3-Output Programmable Buck Regulator

XR77103
Applications Information (Continued)
Stop Condition
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while
the SCL line is high, as shown in Figure 41.
Figures 42 and 43 illustrate a write and a read cycle. For complete details, see the I²C-bus specifications.
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
A
DATA
A
P
NOTES:
White Block = host to XR77103, Orange Block = XR77103 to host.
Figure 42. Master Writes to Slave
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
A
S
SLAVE
ADDRESS
R
A
DATA
NA
P
NOTES:
White Block = host to XR77103, Orange Block = XR77103 to host.
Figure 43. Master Reads from Slave
Slave Address
The slave address is one byte of data which is used as the unique identifier. The first 7 bits of the slave address are hard-
coded and the least significant bit (LSB) of the slave address byte is the read/write (R/W) bit which is used to determine
whether a command is a write command or a read command. The slave address is the first byte of information sent to the
device after the START condition. Table below shows the possible slave addresses for the XR77103.
Device
XR77103
Address (A0 = Low) Address (A0 = High)
0x74
0x75
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1
1
1
0
1
0
A0 R/W
Register Map
Register
Address
Register Name
00h
V_BUCK1
01h
V_BUCK2
02h
V_BUCK3
03h Soft-start and Delay 1
04h Soft-start and Delay 2
05h Soft-start and Delay 3
06h Current Limit 1
07h Current Limit 2
08h Current Limit 3
09h
Switching Frequency
and Phase
0Ah PWR
Bit 7
EXT1
EXT2
EXT3
-
-
-
-
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Factory Default
NVM Value
V_BUCK1 [6:0]
V_BUCK2 [6:0]
00h
V_BUCK3 [6:0]
DLY1 [2:0]
-
SST1 [2:0]
DLY2 [2:0]
-
SST2 [2:0]
15h
DLY3 [2:0]
-
SST3 [2:0]
-
-
-
-
LIM1 [2:0]
-
-
-
-
LIM2 [2:0]
05h
-
-
-
-
LIM3 [2:0]
PHS
[1:0]
-
FRQ
[4:0]
-
-
-
-
42h
UV
-
-
PSM
Buck3 Buck2 Buck1
7Fh
REV1B
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