XR77103 Datasheet, PDF (19/28 Pages) Exar Corporation – 3-Output Programmable Buck Regulator

XR77103
Applications Information (Continued)
Thermal Design
Proper thermal design is critical in controlling device
temperatures and in achieving robust designs. There are
a number of factors that affect the thermal performance.
One key factor is the temperature rise of the devices in
the package, which is a function of the thermal resistances
of the devices inside the package and the power being
dissipated.
The thermal resistance of the XR77103 (30°C/W) is specified
in the Operating Conditions section of this datasheet.
The θ_JA thermal resistance specification is based on the
XR77103 evaluation board operating without forced airflow.
Since the actual board design in the final application will be
different, the thermal resistances in the final design may be
different from those specified.
The package thermal derating and power loss curves are
shown in Figures 21 through 33. These correspond to input
voltages of 12V and 5V, and 500kHz and 1MHz switching
frequencies.
Layout Guidelines
Proper PCB layout is crucial in order to obtain a good
thermal and electrical performance.
For thermal considerations it is essential to use a number
of thermal vias to connect the central thermal pad to the
ground layer(s).
In order to achieve good electrical and noise performance
following steps are recommended:
■■ Place the output inductor close to the LX pins and
minimize the area of the connection. Doing this
on the same layer is advisable.
■■ Central thermal pad, PGND, shall be connected
as many layers as possible for good thermal
performance. The input capacitors connected
between VIN1, VIN2, VIN3 and PGND represent
an AC current loop which should be minimized.
PGND should connect to the system ground with
vias placed at the output filtering capacitors
■■ The AC current loop created by the output
inductors, output filtering capacitors, and the
regulator pins should also be minimized. However
this loop is less critical than the input capacitors.
■■ GND, AGND, DGND can all be connected at the
device and be connected to system ground at the
output capacitor.
■■ Compensation networks shall be placed close to
the pins and referenced to AGND.
■■ VCC bypass capacitor shall be placed close to
the pin and connected to AGND.
I2C Bus Interface
The XR77103 features an I²C compatible, 2-wire serial
interface consisting of a serial-data line (SDA) and a serial
clock line (SCL). SDA and SCL facilitate communication
between the IC and the master device at clock rates up to
400kHz. The I²C interface follows all standard I²C protocols.
Some information is provided below. For additional
information, refer to the I²C-bus specifications.
SDA
SCL
S
START Condition
P
STOP Condition
Figure 41. I²C Start and Stop Conditions
Start Condition
The master initiates data transfer by generating a start
condition. The start condition is when a high-to-low transition
occurs on the SDA line while SCL is high, as shown in
Figure 41.
Slave Address Cycle
After the start condition, the first byte sent by the master is
the 7-bit address and the read/write direction bit R/W on the
SDA line. If the address matches the XR77103’s internal
fixed I²C slave address, the XR77103 will respond with an
acknowledge by pulling the SDA line low for one clock cycle
while SCL is high.
Data Cycle
After the master detects this acknowledge, the next byte
transmitted by the master is the sub-address. This 8-bit
sub-address contains the address of the register to access.
The XR77103 Register Map is on page 20.
REV1B
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