XR77103 Datasheet, PDF (18/28 Pages) Exar Corporation – 3-Output Programmable Buck Regulator

XR77103
Applications Information (Continued)
Power Good
The PGOOD pin is an open drain output. The PGOOD
pin is pulled low when any buck converter is pulled below
85% of the nominal output voltage. The PGOOD is pulled
up when selected buck converters’ outputs are more than
90% of their nominal output voltage and the PGOOD reset
timer expires. The polarity of the PGOOD is active high.
The PGOOD reset time is determined by following equation.
Figure 40 shows the relationship between switching
ftrheequsewnitccyhianngdfrtehqeuPeGncO_VyOO_XisD=1r0eM_.s_{8HeVzt ,x}timth₁ee._+PF^RR_Gor¹²_{OeOxaDmrpelsee, twthimeen}
is 1s.
t_RP
=
1
f_SW
x
10⁶
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
0.5
1.0
1.5
2.0
Switching Frequency (MHz)
Figure 40. PGOOD Reset Time vs. f_SW
Selectable UVLO Threshold
The threshold for UVLO is selectable (7V/4.2V). When input
voltage is higher, 9V and 12V for example, both settings
can be used. However, when the input voltage is 5V,
the UVLO setting must be 4.2V.
Supply Voltage for Data Programming and
Writing to NVM
V_L is the supply voltage for I²C interface and is required for
all I²C transactions. The V_L pin can be left floating if the I²C
interface is not used.
To write data to NVM, V_IN must be 8V or higher.
The state of the nWR pin determines where the data
gets written to. If the nWR pin is pulled low to ground, the
data is written to the NVM. The I²C write transaction can
start immediately after the nWR pin has been pulled low.
A 100ms delay shall be added in between consecutive
I²C writes to the NVM. After each byte is written to
NVM location, the data gets automatically transferred to the
run time equivalent register. If the nWR pin is pulled high
or left floating, the data gets written to run time registers.
In case V_IN is below 8V, writing to NVM is not possible in
which case the nWR pin must be pulled high or left floating
to assure reliable writing to run time registers.
V_L
3.3V
3.3V
V_IN
EN nWR I²C Write Behavior
≥8V
LOW
LOW
Write to NVM, values loaded
to run-time registers
≥8V HIGH LOW Not supported
3.3V
3.3V
3.3V
3.3V
≤8V
4.5V to
14V
4.5V to
14V
4.5V to
14V
X
LOW
HIGH
X
LOW
HIGH
Write has no effect
Write to run-time registers
with offsets > 02h
HIGH Not supported
HIGH
Write to run-time registers
with offsets ≤ 02h
In addition, the nWR pin state determines where data gets
read from in case a read I²C command is transmitted on
the bus. When initiating read transaction while the nWR pin
is pulled high or left floating, the data is read from the run
time registers. Reading run time registers can be done at
any time.
On the other hand if the nWR pin is pulled low at the
time when a read transaction is sent, the data is read
from NVM. It is recommended not to permanently pull
the nWR pin low. In designs where the nWR pin is pulled
low permanently, the host shall not initiate read transaction
while channels are enabled. Failing to do so will cause
regulation interruption. Reading in this scenario shall be
done while EN is low and channels are shut down.
V_L
3.3V
3.3V
3.3V
V_IN
4.5V to
14V
4.5V to
14V
4.5V to
14V
EN
LOW
HIGH
X
nWR I²C Read Behavior
LOW
Read from NVM (when all
channels are disabled)
LOW Not supported
HIGH Read from run-time registers
At power-on, the run-time registers are loaded with
their default values from the NVM. This process takes
approximately 200µs. No I²C operation should be performed
during this time.
REV1B
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