XR16L2750 Datasheet, PDF (20/49 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO

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XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
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TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
IER RD/WR 0/
0/
0/
0/
Modem RX Line TX
RX
CTS Int. RTS Int. Xoff Int.
Enable Enable Enable
Sleep
Mode
Enable
Stat. Int.
Enable
Stat. Empty Data
Int.
Int
Int.
Enable Enable Enable
010
010
ISR
FCR
RD FIFOs FIFOs
0/
0/
INT
INT
INT
INT ^{LCR[7] = 0}
Enabled Enabled
INT
INT
Source Source
Source Source Source Source
Bit-3 Bit-2 Bit-1 Bit-0
Bit-5 Bit-4
WR RXFIFO RXFIFO 0/
0/
Trigger Trigger
TXFIFO TXFIFO
Trigger Trigger
DMA
Mode
Enable
TX
RX FIFOs
FIFO FIFO Enable
Reset Reset
011
100
LCR RD/WR Divisor Set TX Set Par- Even
Enable Break
ity
Parity
Parity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
MCR RD/WR
0/
BRG
Pres-
caler
0/
IR Mode
ENable
0/
XonAny
Internal OP2#/INT Rsrvd RTS# DTR#
Lopback Output _(OP1#) Output Output
Enable Enable
Control Control
101
110
111
111
LSR RD RX FIFO THR & THR
Global TSR Empty
Error Empty
MSR RD
CD#
Input
SPR RD/WR Bit-7
RI#
Input
Bit-6
DSR#
Input
Bit-5
EMSR WR
16X
Sam-
pling
Rate
Mode
LSR
Error
Inter-
rupt.
Imd/Dly#
Auto
RTS
Hyst.
bit-3
RX RX Fram- RX
Break ing Error Parity
Error
RX
Over-
run
Error
RX
Data
Ready
LCR[7] = 0
CTS#
Input
Delta
CD#
Delta Delta Delta
RI# DSR# CTS#
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0 LCR[7] = 0
FCTR[6]=0
Auto
RTS
Hyst.
bit-2
Auto
RS485
Output
Inversion
Rsrvd
Rx/Tx
FIFO
Count
Rx/Tx
FIFO
Count
LCR[7] = 0
FCTR[6]=1
1 1 1 FLVL RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
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