XR16L2750 Datasheet, PDF (18/49 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO

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XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
interrupt is pending from channel A or B. The 2750 will stay in the sleep mode of operation until it is disabled by
setting IER bit-4 to a logic 0.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. Also, make sure the RX A/B inputs are idling at logic 1 or “marking”
condition during sleep mode to avoid receiving a “break” condition upon the restart. This may occur when the
external interface transceivers (RS-232, RS-485 or another type) are also put to sleep mode and cannot
maintain the “marking” condition. To avoid this, the system design engineer can use a 47k ohm pull-up resistor
on the RXA and RXB pins.
2.21 Internal Loopback
The 2750 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal. Also, Auto RTS/
CTS is not supported during internal loopback.
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B
Transmit Shift Register
(THR/FIFO)
VCC
MCR bit-4=1
Receive Shift Register
(RHR/FIFO)
VCC
RTS#
CTS#
VCC
DTR#
DSR#
RI#
OP1#
VCC
OP2#
CD#
TXA/TXB
RXA/RXB
RTSA#/RTSB#
CTSA#/CTSB#
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
OP2A#/OP2B#
CDA#/CDB#
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