XR16L2750 Datasheet, PDF (17/49 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO

XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
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2.19 Infrared Mode
The 2750 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGH-
pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See Figure 12 below.
The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. When the infrared feature
is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level
of logic zero from a reset and power up, see Figure 12.
Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream. However, this is not true with some
infrared modules on the market which indicate a logic 0 by a light pulse. So the 2750 has a provision to invert
the input polarity to accommodate this. In this case user can enable FCTR bit-2 to invert the input signal.
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
C h a ra cte r
Data Bits
TX Data ^{0 1 0 1 0 0 1 1 0 1}
Transm it
IR Pulse
(TX Pin)
Receive
IR Pulse
(RX pin)
RX Data
Bit Tim e
3/16 Bit Tim e
1/2 Bit Tim e
IrEncoder-1
Bit Time
1/16 Clock Delay
0 1 0 1 0 0 11 0 1
Data Bits
Character
IRdecoder-1
2.20 Sleep Mode with Auto Wake-Up
The 2750 supports low voltage system designs, hence, a sleep mode is included to reduce its power
consumption when the chip is not actively used. With EFR bit-4 and IER bit-4 of both channels enabled (set to
a logic 1), the 2750 DUART enters sleep mode when no interrupt is pending for both channels. The 2750 stops
its crystal oscillator to further conserve power in the sleep mode. User can check the XTAL2 pin for no clock
output as an indication that the device has entered the sleep mode. The 2750 resumes normal operation by
any of the following: a receive data start bit transition (logic 1 to 0), a change of logic state on any of the modem
or general purpose input pins: CTS#, DSR#, CD#, RI# or a transmit data byte is loaded to the THR/FIFO by the
user. If the 2750 is awakened by one of the above conditions, it will return to the sleep mode automatically after
all interrupting condition have been serviced and cleared. If the 2750 is awakened by the modem inputs, a read
to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an
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