XRP7720 Datasheet, PDF (15/28 Pages) Exar Corporation – Quad Output Universal Customizable PMIC with PFM

XRP7720
Quad Output Universal Customizable PMIC with PFM
The XRP7720 DPWM includes a special delay
timing loop that gives a timing resolution that
is 16 times the master oscillator frequency
(103MHz) for a timing resolution of 607ps for
both the driver pulse width and dead time
delays. The DWPM creates and drives the
Gate High (GH) and Gate Low (GL) signals.
The maximum and minimum on times and
dead time delays are programmable by
configuration resisters.
PFM mode loop
The XRP7724 has a PFM loop that can be
enabled to improve efficiency at light loads.
By reducing switching frequency and operating
in the discontinuous conduction mode (DCM),
both switching and I²R losses are minimized.
Figure 12 shows a functional diagram of the
PFM logic.
# Cycles Reg
Default = 20
PFM Current
Threshold Reg
IADC
VOUT
VREF HIGH
VREF
CHx Fsw
A
A<B
B
+
-
-
+
COUNTER
Clk
Clear
A
A<B
B
PFM EXIT
SQ
RQ
PWM MODE
PFM MODE
TRIGGER PULSE
-
VREF LOW
+
Figure 12 PFM Enter/Exit Functional Diagram
The PFM loop works in conjunction with the
PWM loop and is entered when the output
current falls below a programmed threshold
level for a programmed number of cycles.
When PFM mode is entered, the PWM loop is
disabled and instead, the scaled output
voltage is compared to Vref with a window
comparator. The window comparator has three
thresholds; normal (Vref), high (Vref +
%high) and low (Vref - %low). The %high and
%low values are programmable and track
Vref.
In PFM mode, the normal comparator is used
to regulate the output voltage. If the output
voltage falls below the Vref level, the
comparator is activated and triggers the
DPWM to start a switching cycle. When the
high side FET is turned on, the inductor
current ramps up which charges up the output
capacitors and increasing their voltage. After
the completion of the high side and low side
on-times, the lower FET is turned off to inhibit
any inductor reverse current flow. The load
current then discharges the output capacitors
until the output voltage falls below Vref and
the normal comparator is activated this then
triggers the DPWM to start the next switching
cycle. The time from the end of the switching
cycle to the next trigger is referred to as the
dead zone.
When PFM mode is initially entered the
switching duty cycle is the same that it was in
PWM mode. The result is the inductor ripple
current will remain the same as it was in PWM
mode. During operation the PFM duty cycle is
calculated based on the ratio of the output
voltage to VCC. This method ensures that the
output voltage ripple is well controlled and is
much lower than in other architectures which
use a “burst” methodology.
If the output voltage ever goes outside the
high/low windows, PFM mode is exited and the
PWM loop is reactivated.
Although the PFM mode does a good job in
improving efficiency at light load, at very light
loads the dead zone time can increase to the
point where the switching frequency can enter
the audio hearing range. When this happens
some components, like the output inductor
and ceramic capacitors, can emit audible
noise. The amplitude of the noise depends
mostly on the board design and on the
manufacturer and construction details of the
components. Proper selection of components
can reduce the sound to very low levels. In
general Ultrasonic Mode is not used unless
required as it reduces light load efficiency.
Ultrasonic Mode
Ultrasonic mode is an extension of PFM to
ensure that the switching frequency never
enters the audible range. When this mode is
entered, the switching frequency is set to
30kHz and the duty cycle of the upper and
lower FETs, which are fixed in PFM mode, are
decreased as required to keep the output
© 2014 Exar Corporation
15/28
Rev. 1.0.0