XR10910 Datasheet, PDF (15/19 Pages) Exar Corporation – 16:1 Sensor Interface

XR10910
Offset Correction
The XR10910 has a 10-bit offset correction DAC that can be
used to provide digital calibration on each of the 16 inputs.
Only the offset voltage of the active channel is applied to
the PGA.
The DAC offset of each channel is controlled by the I2C
compatible interface. At any time, the master can read or
write to any of the DAC offset registers. The DAC offset for
each channel is set via I2C using the register addresses
0x20 thru 0x2F followed by another two bytes of data to
set the polarity and value of the offset voltage. Refer to the
Register List in Table 1.
A ±560mV offset correction range is available. The full
range of the DAC offset is only available at a gain of 2. At
higher gains, the output voltage range of the XR10910 will
be exceeded if the full range of the DAC offset is used. The
internal 10-bit DAC allows 1,024 different offset voltage
settings between 0mV and 560mV. The polarity of the
offset correction is set with an additional bit. The unit offset
is determined by the following:
Unit offset ⁼
Total Offset
DAC output levels
=
560mV
1024
= _547nV
Step 5
9
XR10910 sends acknowledge
A
Since a DAC Offset register was accessed, the XR10910
is expecting another two bytes of data from the master to
complete the command. Refer to the “Byte of Parameter”
column in the Register List (Table 1). D0 thru D9 are used
to set the offset voltage and D10 is used to set the sign of
the offset voltage, 0 = positive and 1 = negative. Refer to the
DAC Offset register list in Table 2.
To determine what DAC output level corresponds to 75mV,
use the following equation:
DAC Output Level ⁼
Desired Offse t
Unit Offset
=
75mV
547 nV
= ₁₃₇
A decimal value of 137 corresponds to 75mV. Therefore:
■■ 0x89 (hex) or 0 00 1000 1001 (binary) applies a +75mV
offset
■■ 0x489 (hex) or 1 00 1000 1001 (binary) applies a -75mV
offset
From Table 3:
■■ 0x00 (hex) or 0 00 0000 0000 (binary) applies a 0mV offset
■■ 0x3FF (hex) or 0 11 1111 1111 (binary) applies a +560mV
offset
■■ 0x7FF (hex) or 1 11 1111 1111 (binary) applies a -560mV
offset
Step 6
15 14 13 12 11 10
9
8
Master sends 1^st byte of
DAC offset register data to 0 0 0 0 0 0
0
0
select an offset of +75mV
2 MSBs of 10-bit
Sign DAC output level that
corresponds to 137 (0x89)
Each DAC output level provides an additional 547µV of
offset. To determine what DAC output level corresponds to
a specific desired offset, use the following equation:
See example below for additional information.
Example: The example below illustrates how to set the DAC
offset for channel 7 to a value of 75mV.
To start communication with the XR10910, repeat steps 1-3
as shown in the Inputs and Input Selection section on page
11.
Step 4
Master sends address of register to access
76543210
00100110
DAC7 register address = 0x26
Step 7
9
XR10910 sends acknowledge
A
Step 8
76543210
Master sends 2^nd byte of DAC offset register data
to select an offset of +75mV
1
0
0
0
1
0
0
1
8 LSBs of 10-bit DAC output level
that corresponds to 137 (0x89)
Step 9
9
XR10910 sends acknowledge
A
Step 10
0
Master sends stop condition
P
White Block = host to XR10910
Red Block = XR10910 to host
Grey Block = Notes
© 2014-2015 Exar Corporation
15 / 19
exar.com/XR10910
Rev 1B