XR10910 Datasheet, PDF (13/19 Pages) Exar Corporation – 16:1 Sensor Interface

XR10910
I²C Bus Interface
The I²C-bus interface consists of two lines: serial data (SDA)
and serial clock (SCL). The XR10910 works as a slave and
supports both standard mode transfer rates (100 kbps) and
fast mode transfer rates (400 kbps) as defined in the I²C-
Bus specification. The I²C-bus interface follows all standard
I²C protocols. Some information is provided below, for
additional information, refer to the I²C-bus specifications.
Figures 4 and 5 illustrate a write and a read cycle. For
complete details, see the I2C-bus specifications.
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
A nDATA A
P
White Block = host to XR10910
Red Block = XR10910 to host
Figure 4: Master Writes to Slave (XR10910)
Figure 3: I²C Start and Stop Conditions
The basic I²C access cycle for the XR10910 consists of:
■■ A start condition
■■ A slave address cycle
■■ Zero, one, or two data cycles - depending on the XR10910
register accessed
■■ A stop condition
Start Condition - The master initiates data transfer by
generating a start condition. The start condition is when a
high-to-low transition occurs on the SDA line while SCL is
high, as shown in Figure 3.
Slave Address Cycle – After the start condition, the first
byte sent by the master is the 7-bit address and the read/
write direction bit R/W on the SDA line. If the address
matches the XR10910’s internal fixed address, the XR10910
will respond with an acknowledge by pulling the SDA line
low for one clock cycle while SCL is high.
Data Cycle – After the master detects this acknowledge,
the next byte transmitted by the master is the sub-address.
This 8-bit sub-address contains the address of the register
to access. The XR10910 Register List is shown in Table
1. Depending on the register accessed, there will be up to
two additional data bytes transmitted by the master. Refer
to the “Byte of Parameter” column in the Register Table. The
XR10910 will respond to each write with an acknowledge.
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
A
S
SLAVE
ADDRESS
R
A
nDATA
A
LAST
DATA
NA
P
White Block = host to XR10910
Red Block = XR10910 to host
Figure 5: Master Reads from Slave (XR10910)
I²C Bus Addressing
The XR10910 uses a 7-bit address space. For the standard
XR10910, the default address is 0x67 (0110 111).
I2C Address
0x67 (0110 111x)
Orderable Part#
XR10910IL40TR-F
Table 4: XR10910 I²C Address Map
A read or write transaction is determined by bit-0 of the
slave address, (shown as an “x” in Table 1 above). If bit-0 is
’0,’ then it is a write transaction. If bit-0 is ’1,’ then it is a read
transaction.
An I2C sub-address is sent by the I2C master following
the slave address. The sub-address contains the XR10910
register address being accessed. Table 1 illustrates the
available XR10910 register addresses.
After the last read or write transaction, the I2C-bus master
will set the SCL signal back to its idle state (HIGH).
Stop Condition – To signal the end of the data transfer,
the master generates a stop condition by pulling the SDA
line from low to high while the SCL line is high, as shown in
Figure 3.
© 2014-2015 Exar Corporation
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exar.com/XR10910
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