XRT7295AT Datasheet, PDF (14/18 Pages) Exar Corporation – DS3/Sonet STS-1 Integrated Line Receiver

XRT7295AT
TIMING CHARACTERISTICS
Test Conditions:
5V ±10%
All Timing Characteristics are Measrured with 10pF Loading,
-40°C ± T_A ± +85°C, V_DD =
Symbol
tRCH1RCH2
tRCL2RCL1
tRCHRDV
Parameter
Clock Rise Time (10% - 90%)
Clock Fall Time (10% - 90%)
Receive Propagation Delay¹
Clock Duty Cycle
Min
Typ
Max
Unit
4
ns
4
ns
0.6
3.7
ns
45
50
55
%
Table 7. System Interface Timing Characteristics
R(RCCLK)
RPDATA
OR
RNDATA
(RD)
tRCHRDV
tRDVRCL
tRCL2RCL1
tRCLRDX
Figure 11. Timing Diagram for System Interface
tRCH1RCH2
BOARD LAYOUT CONSIDERATIONS
Power Supply Bypassing
Figure 12 illustrates the recommended power supply
bypassing network. A 0.1mF capacitor bypasses the
digital supplies. The analog supply V_DDA is bypassed by
using a 0.1mF capacitor and a shield bead that removes
significant amounts of high-frequency noise generated by
the system and by the device logic. Good quality,
high-frequency (low lead inductance) capacitors should
be used. Finally, it is most important that all ground
connections be made to a low-impedance ground plane.
Receive Input
The connections to the receive input pin, R_IN, must be
carefully considered. Noise-coupling must be minimized
along the path from the signal entering the board to the
input pin. Any noise coupled into the XRT7295AT input
directly degrades the signal-to-noise ratio of the input
signal and may degrade sensitivity.
PLL Filter Capacitor
The PLL filter capacitor between pins LPF1 and LPF2
must be placed as close to the chip as possible. The LPF1
and LPF2 pins are adjacent, allowing for short lead
lengths with no crossovers to the external capacitor.
Noise-coupling into the LPF1 and LPF2 pins may
degrade PLL performance.
Handling Precautions
Although protection circuitry has been designed into this
device, proper precautions should be taken to avoid
exposure to electrostatic discharge (ESD) during
handling and mounting.
Rev.1.20
14