XRT7295AT Datasheet, PDF (11/18 Pages) Exar Corporation – DS3/Sonet STS-1 Integrated Line Receiver

XRT7295AT
JITTER ACCOMMODATION
Under all allowable operating conditions, the jitter
accommodation of the XRT7295AT device exceeds all
system requirements for error-free operation
(BER<1E^-9). The typical (V_DD = 5V, T = 25°C, DSX-3
nominal signal level) jitter accommodation for the
XRT7295AT is shown in Figure 10.
FALSE-LOCK IMMUNITY
False-lock is defined as the condition where a PLL
recovered clock obtains stable phase-lock at a frequency
not equal to the incoming data rate. The XRT7295AT
device uses a combination frequency/phase-lock
architecture to prevent false-lock. An on-chip frequency
comparator continuously compares the EXCLK reference
to the PLL clock. If the frequency difference between the
EXCLK and PLL clock exceeds approximately ±0.5%,
correction circuitry forces re-acquisition of the proper
frequency and phase.
ACQUISITION TIME
If a valid input signal is assumed to be already present at
R_IN, the maximum time between the application of device
power and error-free operation is 20ms. If power has
already been applied, the interval between the application
of valid data (or the action of valid data following a loss of
signal) and error-free operation is 4ms.
LOSS-OF-LOCK DETECTION
As stated above, the PLL acquisition aid circuitry monitors
the PLL clock frequency relative to the EXCLK frequency.
The RLOL alarm is activated if the difference between the
PLL clock and the EXCLK frequency exceeds
approximately ±0.5%.
This will not occur until at least 250 bit periods after loss of
input data.
1
0
-1
-2
-3
-4
-5
100
PEAK = 0.05dB
f3dB = 205kHz
500 1K 5K 10K 50K100K 500K
Frequency (Hz)
Figure 9. Typical PLL Jitter Transfer
Characteristic
40
10
G.824
1.0
0.1
1
TR-TSY-000499
Category 2
TR-TSY-000499
Category 1
PUB 54014
XRT7295AT Typical
XRT7295AT Typical
Jitter
Frequency
(Hz)
Jitter
Amplitude
(U.I.)
5k
10
10k
5
60k
1
300k
0.5
1M
0.4
10
100
1K
10K
100K
Sinewave Jitter Frequency (Hz)
1000K
Figure 10. Input Jitter Tolerance at DSX-3 Level
Rev.1.20
11