XRT71D04 Datasheet, PDF (14/22 Pages) Exar Corporation – 4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER

XRT71D04
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4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
FIGURE 6. A TYPICAL CHANNEL_N OF THE XRT71D04 CONFIGURED TO OPERATE IN THE HOST MODE
ICT
RCLK_n
RPOS_n
RNEG_n
Jittery
Clock
Timing Control Block /
Phase locked Loop
Smoothed
Clock
MClkn
Write Clock
Read Clock
16/32 Bit FIFO
RRCLK_n
RRPOS_n
RRNEG_n
RRCLKES
FL_n
HOST
Reset
Microprocessor Serial
Interface
CS SDI SDO SClk
The XRT71D04 DS3/E3 Jitter Attenuator IC consists
of the following functional blocks:
• The Jitter-Attenuator PLL
• Timing Control Block
• The 2-Channel 16/32 Bit FIFO
• Serial Microprocessor Interface
1.0 JITTER ATTENUATOR PLL
1.1 BACKGROUND INFORMATION
1.1.1 Definition of Jitter
One of the most important and least understood mea-
sures of clock performance is jitter. The International
Telecommunication Union defines jitter as short term
variations of the significant instants of a digita signal
from their ideal positions in time. Jitter can occur due
to any of the following:
1) Imperfect timing recovery circuit in the system
2) Cross-talk noise
3) Inter-symbol interference/Signal Distortion
1.1.2 SONET STS-1 to DS3 Mapping
SONET equipment jitter criteria are specified as:
i) Jitter Transfer
ii) Jitter Tolerance
iii) Jitter Generation
1.2 JITTER TRANSFER CHARACTERISTICS
The primary purpose of jitter transfer requirements is
to prevent performance degradations by limiting the
accummulation of jitter through the system such that
it does not exceed the network interface jitter require-
ments. Thus, it is more important that a system meet
the jitter transfer criteria for relatively high input jitter
amplitudes. The jitter transferred through the system
must be under the jitter mask for any input jitter ampli-
tude within the range as shown in Figure 7
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