XR22804 Datasheet, PDF (13/47 Pages) Exar Corporation – Hi-Speed USB to 10/100 Ethernet Bridge with 4 UARTs

XR22804
ICMP checksum offload over IPV4 and IPV6 as well as header checksum offload in IPV4. On chip RAM provides all
required packet buffering.
In Windows OS, using the Exar custom Ethernet driver, the properties dialog, advanced properties can be used to set the
pause frame flow control, speed and duplex, auto-negotiation, checksum offload, and Ethernet remote wakeup settings. By
default, the Ethernet MAC will honor incoming pause frames sent by a peer Ethernet device, but will not generate pause
frames. Auto-MDIX is always enabled.
Ethernet Remote Wakeup
If the XR22804 hub is configured as a self-powered device and has Ethernet remote wakeup enabled, the XR22804 will
request the USB host to resume in response to a magic packet or a link state change on the Ethernet port. When the USB
host is suspended, the Ethernet Phy remains active and the XR22804 is able to both meet USB suspend mode power
requirements as well as respond to magic packet and link state changes.
The magic packet is an Ethernet packet with specific content, i.e. 6 bytes of 0xFF, followed by 16 repetitions of the target
MAC address (MAC address of the XR22804 device). This content can occur anywhere in the incoming packet payload.
The link state change will wake the USB host if the link is down when the USB host is suspended and then the link goes up,
or if the link is up when the USB host is suspended and then the link goes down.
UART
The UART can be configured via USB control transfers from the USB host. The UART transmitter and receiver sections are
described separately in the following sections. At power-up, the XR22804 will default to 9600 bps, 8 data bits, no parity bit,
1 stop bit, and no flow control. If a standard CDC-ACM driver accesses the XR22804, defaults will change. See Remote
Wakeup section on page 11.
UART transmitter
The transmitter consists of a 1024-byte TX FIFO and a Transmit Shift Register (TSR). Once a bulk-out packet has been
received and the CRC has been validated, the data bytes in that packet are written into the TX FIFO of the specified UART
channel. Data from the TX FIFO is transferred to the TSR when the TSR is idle or has completed sending the previous data
byte. The transmitter sends the start bit followed by the data bits (starting with the LSB), inserts the proper parity-bit if
enabled, and adds the stop-bit(s). The transmitter can be configured for 7 or 8 data bits with or without parity or 9 data bits
without parity. If 9 bit data is selected without wide mode, the 9th bit will always be ’0’.
UART transmitter - Wide mode
When both 9 bit data and wide mode are enabled, two bytes of data must be written. The first byte that is loaded into the TX
FIFO are the first 8 bits (data bits 7-0) of the 9-bit data. Bit-0 of the second byte that is loaded into the TX FIFO is bit-8 of the
9-bit data. The data that is transmitted on the TX pin is as follows: start bit, 9-bit data, stop bit. Use the TX_WIDE_MODE
register to enable transmit wide mode.
UART receiver
The receiver consists of a 1024-byte RX FIFO and a Receive Shift Register (RSR). Data that is received in the RSR via the
RX pin is transferred into the RX FIFO. Data from the RX FIFO is sent to the USB host in response to a bulk-in request.
Depending on the mode, error / status information for that data character may or may not be stored in the RX FIFO with the
data.
UART receiver - Normal mode with 7 or 8-bit data
Data that is received is stored in the RX FIFO. Any parity, framing or overrun error or break status information related to the
data is discarded. Receive data format is shown in Figure 1.
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