XR18910 Datasheet, PDF (13/19 Pages) Exar Corporation – 8:1 Sensor Interface Analog Front End

REV. 1.0.0
XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.0 FUNCTIONAL DESCRIPTIONS
1_A.1 _ppCP_lU_iI_cnte_arfa_tc_ie_{on Information (Continued)}
The XR20M1280 can operate with either an I²C-bus interface or an SPI interface. The CPU interface is
selected via the I2C/SPI# input pin.
I C ²
1.1.1
B_Iu2_Cs_-buI_sn_Int_tee_rfr_af_ca_e ce
Th^Te^hI²C^e-b^Iu²s^Cint^-e^brfa^uce^sisⁱcⁿom^tepli^ra^fn^at w^cit^eh th^ce^oStⁿan^sdaⁱr^sd-^tm^sod^oe^fan^td^wFa^ost-^lmⁱⁿod^ee^sI²C^: -^sbu^es ^rsp^iaec^lifi^dca^atio^tn^as. T⁽h^Se ^DI²C^A-bu⁾s
and serial clock (SCL). The XR18910 works as a slave and ^{interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock}
and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400
kb_sp_us. _pTh_pe_ofir_rst_tsbyte_bs_oen_tt_hby_sa_tn_aI²_nC-_dbu_as_rm_das_mter _oco_dnta_eins_tra_ast_nart_sb_fit_e(S_rD_rA_atr_ta_ens_sitio₍n₁fr₀om₀HI_kG_bH _pto_sLO₎ W_aw_nh_den
fast mode transfer rates (400 kbps) as defined in the I C- ^{SCL is HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the2 sub-}
address that contains the address of the register to access. The XR20M1280 responds to each write with an
Bus specification. The I C-bus interface follows all standard ^{acknowledge (SDA driven LOW by XR20M12280 for one clock cycle when SCL is HIGH). If the TX FIFO is full,}
the XR20M1280 will respond with a negative acknowledge (SDA driven HIGH by XR20M1280 for one clock
cy_Ic2l_Ce whe_pn_rS_oCL_tois_cH_oIG_lH_s) _.when_Sthe_oC_mPU_etries_into_fw_ori_rte_mto _athe_tiT_oX_nFIFO_is. Th_pe_rla_ost_vby_idte_ese_dnt by_ba_en I_l²_oC-_wbu_,s m_fa_ost_rer
contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See Figures 3 - 5 below. For
coamdpldeteitdieotanilsa, sleeinthfeoI²rCm-buas stpioecnific,atrioensf.er to the I²C-bus specifications.
FIGURE 3. I²C START AND STOP CONDITIONS
SDA
SCL
S
START condition
P
STOP condition
Figure 21. I²C Start and Stop Conditions
FIGURE 4. MASTER WRITES TO SLAVE (XR20M1280)
The
basic
I^2SC
SLAVE
a^ADc^DRc^Ee^SSss
cycle for the ^{W A}
REGISTER
ADDRESS
A
nDATA
XR18910
AP
consists
of:
White block: host to UART
■■ A start condition ^{Grey block: UART to host}
■■ A slave address cycle
FIGUR_■E_■ 5_Z. M_eA_rS_oT_,ER_oR_nE_eAD_,S_oFR_rO_tM_wSL_oAV_dE _a(X_tR_a20_cM_y1_c28_l0_e)_{s - depending on the XR18910}
S
register accessed SLAVE
ADDRESS
WA
REGISTER
ADDRESS
AS
SLAVE
ADDRESS
RA
nDATA
A
LAST DATA NA P
A stop condition ^Wh■^ite■ ^{block: host to UART}
Grey block: UART to host
Start Condition
The master initiates data transfer by generating a start
condition. The start condition is when a high-to-low transition
occurs on the SDA line whi⁷le SCL is high, as shown in
Figure 21.
Slave Address Cycle
After the start condition, the first byte sent by the master
is the 7-bit address and the read/write direction bit R/W
on the SDA line. If the address matches the XR18910’s
internal fixed address, the XR18910 will respond with an
acknowledge by pulling the SDA line low for one clock cycle
while SCL is high.
Data Cycle
After the master detects this acknowledge, the next byte
transmitted by the master is the sub-address. This 8-bit
sub-address contains the address of the register to access.
The XR18910 Register List is shown in Table 1. Depending
on the register accessed, there will be up to two additional
data bytes transmitted by the master. Refer to the “Byte of
Parameter” column in the Register Table. The XR18910 will
respond to each write with an acknowledge.
XR18910
Stop Condition
To signal the end of the data transfer, the master generates
a stop condition by pulling the SDA line from low to high
while the SCL line is high, as shown in Figure 21.
Figures 22 and 23 illustrate a write and a read cycle. For
complete details, see the I²C-bus specifications.
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
A nDATA A
P
NOTES:
White Block = host to XR18910, Orange Block = XR18910 to host.
Figure 22. Master Writes to Slave (XR18910)
S
SLAVE
ADDRESS
W
A
REGISTER
ADDRESS
A
S
SLAVE
ADDRESS
R
A
nDATA
A
LAST
DATA
NA
P
NOTES:
White Block = host to XR18910, Orange Block = XR18910 to host.
Figure 23. Master Reads from Slave (XR18910)
I²C Bus Addressing
The XR18910 uses a 7-bit address space. For the standard
XR18910, the default address is 0x67 (0110 111). There
are three alternative addresses available to help insure that
the XR18910 can be identified from the other devices on
the I²C-bus. Table 4 shows the different addresses that are
available.
Table 4. XR18910 I²C Address Map
I²C Address
Orderable Part Number
0x67 (0110 111x)
0x66 (0110 110x)
0x65 (0110 101x)
0x64 (0110 100x)
XR18910IL-67
XR18910IL-66
XR18910IL-65
XR18910IL-64
A read or write transaction is determined by bit-0 of the
slave address, (shown as an “x” in the table above). If bit-0
is ’0’, then it is a write transaction. If bit-0 is ’1’, then it is a
read transaction.
An I²C sub-address is sent by the I²C master following the
slave address. The sub-address contains the XR18910
register address being accessed. Table 1 illustrates the
available XR18910 register addresses.
After the last read or write transaction, the I²C-bus master
will set the SCL signal back to its idle state (HIGH).
REV1A
13/19