XR81411 Datasheet, PDF (11/15 Pages) Exar Corporation – Universal Quad Clock - High Frequency LVCMOS/LVDS/LVPECL Clock Synthesizer

XR81411
+VDD/2
Vcc
LVCMOS
Output
Vss
-VDD/2
Z = 50

Scope
Input Stage
The XR81411’s input is designed to be used with a parallel
resonant crystal in the range of 10MHz to 60MHz. It can
also be overdriven by an external single-ended source.
The XR81411 uses a Pierce oscillator circuit that has a vari-
able gain control and selectable capacitor load options on
each of the XTAL pins.
Figure 11: XR81411 Split Supply LVCMOS Output Termination
Output Signal Timing Definitions
The following diagrams clarify the common definitions of
the AC timing measurements.
C1
XTAL_In
XR81411
G
Q
80%
20%
nQ
t_R
80%
V_SWING
20%
t_F
Figure 12: Output Rise/Fall Time and Swing
XTAL_Out
C2
REF
Figure 14: XR81411 Input Stage
The XR81411 input stage also has the ability to use a
startup state that can configure the gain and capacitor load-
ing conditions different from normal operation to improve
crystal startup time.
Q
nQ
t_PW
t_PERIOD
odc =
t_PW
t_PERIOD
x 100%
Figure 13: Output Period and Duty Cycle
PLL Stages
Each of the independent PLLs within the XR81411 can be
configured operate at any of four distinct settings. The PLL
takes the REF output from the Input stage and can produce
any frequency from 10MHz to 800MHz. The PLL can be
configured for integer or fractional operation. The internal
calibration circuitry of the XR81411 will optimize the config-
uration of the VCO, LPF and divider (DSM, N and Output)
settings for the input and output frequencies chosen.
Configurable Attributes
The XR81411 is highly adaptable and can be configured for
many different applications. The device performance of the
input stage, PLL stages and the output stages can be
adjusted (programmed by the factory) to meet any number
of application requirements.
REF
Phase
Detector
Charge
Pump
Lowpass
Filter
Post
Divider
Out’
Control
DSM
N
Divider
Figure 15: XR81411 PLL
© 2014 Exar Corporation
11 / 15
exar.com/XR81411
Rev 1A