XR81411 Datasheet, PDF (10/15 Pages) Exar Corporation – Universal Quad Clock - High Frequency LVCMOS/LVDS/LVPECL Clock Synthesizer

XR81411
Application Information
Termination for LVPECL Outputs
The termination schemes shown in Figure 5 and Figure 6
are typical for LVPECL outputs. Matched impedance layout
techniques should be used for the LVPECL output pairs to
minimize any distortion that could impact your maximum
operating frequency. Figure 7 is an alternate termination
scheme that uses a Y-termination approach.
3.3V
LVPECL
Output
3.3V
3.3V
130
130
50
LVPECL
Input
50
82
82
Termination for LVDS Outputs
The termination schemes shown in Figure 8 and Figure 9
are typical for LVDS outputs. LVDS swing is a small, typi-
cally 350mV, on 1.2V of common mode. The LVDS output
pair needs a 100 resistor across the differential pair as
close to the destination as possible.
3.3V
3.3V
LVDS
Output
50
100
LVDS
Input
50
Figure 8: XR81411 3.3V LVDS Output Termination
Figure 5: XR81411 3.3V LVPECL Output Termination
2.5V
LVPECL
Output
2.5V
2.5V


50
LVPECL
Input
50


2.5V
LVDS
Output
2.5V
50
100
LVDS
Input
50
Figure 9: XR81411 2.5V LVDS Output Termination
Figure 6: XR81411 2.5V LVPECL Output Termination
VDD
VDD
LVPECL
Output
50
LVPECL
Input
50
50
50
For 3.3V systems RTT = 50
For 2.5V systems RTT = 19
RTT
Figure 7: XR81411 Alternate LVPECL Output Termination
Using Y-termination
Termination for LVCMOS Outputs
The termination scheme shown in Figure 10 is typical for
LVCMOS outputs. A split supply approach can be used uti-
lizing the scope’s internal 50 impedance, as shown in
Figure 11.
VDD
VDD
LVCMOS
Output
Z = 50
100
100
High Impedance
scope probe
Figure 10: XR81411 LVCMOS Output Termination
© 2014 Exar Corporation
10 / 15
exar.com/XR81411
Rev 1A