EM639165_07 Datasheet, PDF (61/73 Pages) Etron Technology, Inc. – 8Mega x 16 Synchronous DRAM (SDRAM)

EtronTech
EM639165
Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE ^High
CS#
RAS#
CAS#
WE #
BA0,1
A10
RAx
RBx
RBy
A0~A9,A11
RAx
CAx
RBx
CBx
DQM
RBy
tRP
DQ^Hi-Z
Ax Ax+1 Ax+2Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4Bx+5 Bx+6
Activate
Read
Command Command
Bank A Bank A
Activate
Command
Bank B _{The burst counter wraps}
CBoRmaenmakdaBnFttehduermllbPinuaarsgteet _{cwbohuurensntteotrhpineecrbrauetimrosnet nldetosnegastnhndoisct osanttiinsfuieeds;}
Precharge
Command
Bank B
from the highest order
bursting beginning with the starting address.
page address back to zero
during this time interval
Burst Stop
Command
Activate
Command
Bank B
61
Rev 1.6 Feb. 2007